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  publication number s71pl254/127/064/032j_00 revision a amendment 6 issue date november 22, 2004 advance s71pl254/127/064/032j based mcps stacked multi-chip product (mcp) flash memory and ram 256m/128/64/32 megabit (16/8/4/2m x 16-bit) cmos 3.0 volt-only simultaneous operation page mode flash memory and 64/32/16/8/4 megabit (4m/2m/1m/512k/256k x 16-bit) static ram/pseudo static ram datasheet distinctive characteristics mcp features ? power supply voltage of 2.7 to 3.1 volt ? high performance ?55 ns ? 65 ns (65 ns flash, 70ns psram) ? packages ? 7 x 9 x 1.2mm 56 ball fbga ? 8 x 11.6 x 1.2mm 64 ball fbga ? 8 x 11.6 x 1.4mm 84 ball fbga ? operating temperature ? ?25c to +85c ? ?40c to +85c general description the s71pl series is a product line of stacked multi-chip product (mcp) packages and consists of: ? one or more s29pl (simultaneous read/write) flash memory die ? psram or sram the 256mb flash memory consists of two s29pl127j devices. in this case, ce#f2 is used to access the second flash and no extra address lines are required. the products covered by this document are listed in the table below: note: not recommended for new designs; use psram based mcps instead. flash memory density 32mb 64mb 128mb 256mb psram density 4mb S71PL032J40 8mb S71PL032J80 s71pl064j80 16mb S71PL032Ja0 s71pl064ja0 s71pl127ja0 32mb s71pl064jb0 s71pl127jb0 s71pl254jb0 64mb s71pl127jc0 s71pl254jc0 flash memory density 32mb 64mb sram density (note) 4mb S71PL032J04 8mb S71PL032J08 s71pl064j08
2 s71pl254/127/064/032j based mcps s71pl254/127/064/032j_00_a6 november 22, 2004 preliminary product selector guide 32mb flash memory 64mb flash memory device-model# flash access time (ns) (p)sram density (p)sram access time (ns) psram type package S71PL032J04-0b 65 4m sram 70 sram2 tsc056 S71PL032J04-0f 65 4m sram 70 sram3 tsc056 S71PL032J04-0k 65 4m sram 70 sram4 tsc056 S71PL032J40-0k 65 4m psram 70 psram4 tlc056 S71PL032J40-07 65 4m psram 70 psram1 tsc056 S71PL032J08-0b 65 8m sram 70 sram2 tsc056 S71PL032J80-0p 65 8m psram 70 psram5 tsc056 S71PL032J80-07 65 8m psram 70 psram1 tsc056 S71PL032Ja0-0k 65 16mb psram 70 psram1 tsc056 S71PL032Ja0-0f 65 16mb psram 70 psram3 tsc056 S71PL032Ja0-0z 65 32m psram 70 psram7 tlc056 device-model# flash access time (ns) (p)sram density (p)sram access time (ns) (p)sram type package s71pl064j08-0b 65 8m sram 70 sram2 tlc056 s71pl064j08-0u 65 8m sram 70 sram4 tlc056 s71pl064j80-0k 65 8m psram 70 psram1 tsc056 s71pl064j80-07 65 8m psram 70 psram1 tlc056 s71pl064j80-0p 65 8m psram 70 psram5 tsc056 s71pl064ja0-0z 65 16m psram 70 psram7 tlc056 s71pl064ja0-0b 65 16m psram 70 sram3 tlc056 s71pl064ja0-07 65 16m psram 70 psram1 tlc056 s71pl064ja0-0p 65 16m psram 70 psram7 tlc056 s71pl064jb0-07 65 32m psram 70 psram1 tlc056 s71pl064jb0-0b 65 32m psram 70 psram2 tlc056 s71pl064jb0-0u 65 32m psram 70 psram6 tlc056
november 22, 2004 s71pl254/127/064/032j_00_a6 s71pl254/127/064/032j based mcps 3 preliminary 128mb flash memory 256mb flash memory (2xs29pl127j) device-model# flash access time (ns) psram density psram access time (ns) psram type package s71pl127ja0-9p 65 16m psram 70 psram7 tla064 s71pl127ja0-9z 65 16m psram 70 psram7 tla064 s71pl127ja0-97 65 16m psram 70 psram1 tla064 s71pl127jb0-97 65 32m psram 70 psram1 tla064 s71pl127jb0-9z 65 32m psram 70 psram7 tla064 s71pl127jb0-9u 65 32m psram 70 psram6 tla064 s71pl127jb0-9b 65 32m psram 70 psram2 tla064 s71pl127jc0-97 65 64m psram 70 psram1 tla064 s71pl127jc0-9z 65 64m psram 70 psram7 tla064 s71pl127jc0-9u 65 64m psram 70 psram6 tla064 device-model# flash access time (ns) psram density psram access time (ns) psram type package s71pl254jb0-t7 65 32m psram 70 psram1 fta084 s71pl254jb0-tb 65 32m psram 70 psram2 fta084 s71pl254jb0-tu 65 32m psram 70 psram6 fta084 s71pl254jc0-tb 65 64m psram 70 psram2 fta084 s71pl254jc0-tz 65 64m psram 70 psram7 fta084
4 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information s71pl254/127/064/032j based mcps distinctive characteristics . . . . . . . . . . . . . . . . . . . 1 mcp features ........................................................................................................ 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . .2 32mb flash memory .............................................................................................2 64mb flash memory .............................................................................................2 128mb flash memory ........................................................................................... 3 256mb flash memory (2xs29pl127j) ............................................................... 3 connection diagram (S71PL032J) . . . . . . . . . . . . . .9 connection diagram (s71pl064j) . . . . . . . . . . . . . 10 connection diagram (s71pl127j) . . . . . . . . . . . . . 11 connection diagram (s71pl254j) . . . . . . . . . . . . . 12 special handling instructions for fbga package ................................. 12 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ordering information . . . . . . . . . . . . . . . . . . . . . . . 14 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . .20 tlc056?56-ball fine-pitch ball grid array (fbga) 9 x 7mm package ................................................................................................ 20 tsc056?56-ball fine-pitch ball grid array (fbga) 9 x 7mm package ................................................................................................. 21 tla064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6mm package ............................................................................................ 22 tsb064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package ...........................................................................................23 fta084?84-ball fine-pitch ball grid array (fbga) 8 x 11.6mm ............................................................................................................ 24 s29pl127j/s29pl064j/s29pl032j for mcp general description . . . . . . . . . . . . . . . . . . . . . . . 27 simultaneous read/write operation with zero latency ......................27 page mode features ...........................................................................................27 standard flash memory features ...................................................................27 product selector guide . . . . . . . . . . . . . . . . . . . . .29 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 simultaneous read/write block diagram . . . . . . 31 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 device bus operations . . . . . . . . . . . . . . . . . . . . . . 33 table 1. pl127j device bu s operations ................................ 33 requirements for reading array data .........................................................33 random read (non-page read) ................................................................33 page mode read ..............................................................................................34 table 2. page select .......................................................... 34 simultaneous read/write operation ...........................................................34 table 3. bank select .......................................................... 34 writing commands/command sequences .................................................35 accelerated program operation ...............................................................35 autoselect functions .....................................................................................35 standby mode .......................................................................................................35 automatic sleep mode ......................................................................................36 reset#: hardware reset pin .........................................................................36 table 4. pl127j sector ar chitecture ..................................... 37 table 5. pl064j sector ar chitecture ..................................... 44 table 6. pl032j sector ar chitecture ..................................... 47 table 7. secured silicon sector addresses ............................ 48 autoselect mode ................................................................................................ 49 table 8. autoselect codes (high voltage method) .................. 49 table 9. pl127j boot sector/sector block addresses for protection/ unprotection ..................................................................... 50 table 10. pl064j boot sector/sector block addresses for protection/unprotection ...................................................... 51 table 11. pl032j boot sector/sector block addresses for protection/unprotection ...................................................... 52 selecting a sector protection mode ............................................................. 52 table 12. sector protection schemes ................................... 53 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . 53 sector protection schemes . . . . . . . . . . . . . . . . . 53 password sector protection ........................................................................... 53 wp# hardware protection ............................................................................. 53 selecting a sector protection mode ............................................................. 53 persistent sector protection . . . . . . . . . . . . . . . . 54 persistent protection bit (ppb) ...................................................................... 54 persistent protection bit lock (ppb lock) ................................................. 54 persistent sector protection mode locking bit ....................................... 56 password protection mode . . . . . . . . . . . . . . . . . 56 password and password mode locking bit ................................................ 56 64-bit password .................................................................................................. 57 write protect (wp#) ....................................................................................... 57 persistent protection bit lock ................................................................... 57 high voltage sector protection ..................................................................... 58 figure 1. in-system sector protection/sector unprotection algorithms........................................................................ 59 temporary sector unprotect ........................................................................60 figure 2. temporary sector unprotect operation ................... 60 secured silicon sector flash memory region ...........................................60 factory-locked area (64 words) ............................................................... 61 customer-lockable area (64 words) ....................................................... 61 secured silicon sector protection bits ..................................................... 61 figure 3. secured silicon sector protect verify ...................... 62 hardware data protection ............................................................................. 62 low vcc write inhibit ................................................................................ 62 write pulse ?glitch? protection ............................................................... 62 logical inhibit ................................................................................................... 62 power-up write inhibit ............................................................................... 62 common flash memory interface (cfi) . . . . . . 63 table 13. cfi query identification string .............................. 63 table 14. system interface string ........................................ 64 table 15. device geometry definition ................................... 64 table 16. primary vendor-specific extended query ................ 65 command definitions . . . . . . . . . . . . . . . . . . . . . 66 reading array data ........................................................................................... 66 reset command ................................................................................................. 66 autoselect command sequence .................................................................... 67 enter secured silicon sector/exit se cured silicon sector command se- quence .................................................................................................................... 67 word program command sequence ........................................................... 67 unlock bypass command sequence ........................................................68 figure 4. program operation ............................................... 69 chip erase command sequence ................................................................... 69 sector erase command sequence ................................................................ 70 figure 5. erase operation ................................................... 71 erase suspend/erase resume commands ................................................... 71 command definitions tables ......................................................................... 72 table 17. memory array command definitions ...................... 72 table 18. sector protection command definitions .................. 73 write operation status . . . . . . . . . . . . . . . . . . . . 74 dq7: data# polling ............................................................................................ 75
november 22, 2004 s71pl254/127/064/032j_00_a6 5 advance information figure 6. data# polling algorithm......................................... 76 ry/by#: ready/busy# .......................................................................................76 dq6: toggle bit i ................................................................................................76 figure 7. toggle bit algorithm.............................................. 78 dq2: toggle bit ii .............................................................................................. 78 reading toggle bits dq6/dq2 ..................................................................... 78 dq5: exceeded timing limits ........................................................................79 dq3: sector erase timer .................................................................................79 table 19. write operation status ......................................... 80 absolute maximum ratings . . . . . . . . . . . . . . . . . . 81 figure 8. maximum overshoot waveforms............................. 81 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . .82 industrial (i) devices ......................................................................................... 82 wireless devices ............................................................................................... 82 supply voltages ................................................................................................... 82 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . .83 table 20. cmos compatible ................................................ 83 ac characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .84 test conditions .................................................................................................. 84 figure 9. test setups......................................................... 84 table 21. test specifications ............................................... 84 switching waveforms ....................................................................................... 85 table 22. key to switching waveforms ................................. 85 figure 10. input waveforms and measurement levels............. 85 vcc ramprate .................................................................................................. 85 read operations ................................................................................................ 86 table 23. read-only operations .......................................... 86 figure 11. read operation timings ....................................... 86 figure 12. page read operation timings ............................... 87 reset ...................................................................................................................... 87 table 24. hardware reset (reset#) .................................... 87 figure 13. reset timings..................................................... 88 erase/program operations ............................................................................. 89 table 25. erase and program operations .............................. 89 timing diagrams ................................................................................................. 90 figure 14. program operation timings .................................. 90 figure 15. accelerated program timing diagram .................... 90 figure 16. chip/sector erase operation timings ..................... 91 figure 17. back-to-back read/write cycle timings ................. 91 figure 18. data# polling timings (during embedded algorithms) ............................................ 92 figure 19. toggle bit timings (during embedded algorithms) .. 92 figure 20. dq2 vs. dq6 ...................................................... 93 protect/unprotect . . . . . . . . . . . . . . . . . . . . . . . . 93 table 26. temporary sector unprotect ................................. 93 figure 21. temporary sector unprotect timing diagram.......... 93 figure 22. sector/sector block protect and unprotect timing diagram............................................................................ 94 controlled erase operations ..........................................................................95 table 27. alternate ce# controlled erase and program operations ........................................................... 95 table 28. alternate ce# controlled write (erase/program) operation timings ............................................................. 96 table 29. erase and programming performance .................... 97 bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . 97 type 2 psram features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 product information . . . . . . . . . . . . . . . . . . . . . . . 98 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 power up sequence . . . . . . . . . . . . . . . . . . . . . . . 99 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 99 power up ..............................................................................................................99 figure 23. power up 1 (cs1# controlled) ............................. 99 figure 24. power up 2 (cs2 controlled)................................ 99 functional description . . . . . . . . . . . . . . . . . . . . . 100 absolute maximum ratings . . . . . . . . . . . . . . . . 100 dc recommended operating conditions . . . . . 100 dc and operating characteristics . . . . . . . . . . . 101 common ...............................................................................................................101 16m psram ..........................................................................................................102 32m psram .........................................................................................................102 64m psram .........................................................................................................103 ac operating conditions . . . . . . . . . . . . . . . . . . 103 test conditions (test load and test input/output reference) ........103 figure 25. output load .................................................... 103 acc characteristics (ta = -40c to 85c, v cc = 2.7 to 3.1 v) ........104 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 105 read timings .......................................................................................................105 figure 26. timing waveform of read cycle(1) ..................... 105 figure 27. timing waveform of read cycle(2) ..................... 105 figure 28. timing waveform of read cycle(2) ..................... 105 write timings .....................................................................................................106 figure 29. write cycle #1 (we# controlled)........................ 106 figure 30. write cycle #2 (cs1# controlled) ...................... 106 figure 31. timing waveform of write cycle(3) (cs2 controlled) ............................................................. 107 figure 32. timing waveform of write cycle(4) (ub#, lb# controlled) ..................................................................... 107 psram type 3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . 109 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 109 table 30. dc recommended operating conditions ............... 109 table 31. dc characteristics (t a = -25 c to 85 c, vdd = 2.6 to 3.3v) ............................................................................. 110 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 110 table 32. ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) .............................................. 110 table 33. ac test conditions ............................................. 111 figure 33. ac test loads .................................................. 111 figure 34. state diagram ................................................. 112 table 34. standby mode characteristics .............................. 112 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 35. read cycle 1?addressed controlled ................... 112 figure 36. read cycle 2?cs1# controlled.......................... 113 figure 37. write cycle 1?we# controlled .......................... 113 figure 38. write cycle 2?cs1# controlled ......................... 114 figure 39. write cycle3?ub#, lb# controlled .................... 114 figure 40. deep power-down mode .................................... 115 figure 41. power-up mode ................................................ 115 figure 42. abnormal timing .............................................. 115 psram type 4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 functional description . . . . . . . . . . . . . . . . . . . . . 116 product portfolio ................................................................................................116 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . 117
6 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information operating range ................................................................................................. 117 table 35. dc electrical characteristics (over the operating range) ..............................................117 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . 118 ac test loads and waveforms . . . . . . . . . . . . . 118 figure 43. ac test loads and waveforms ............................ 118 table 36. switching characteristics .....................................119 switching waveforms . . . . . . . . . . . . . . . . . . . . 120 figure 44. read cycle 1 (address transition controlled) ........ 120 figure 45. read cycle 2 (oe# controlled) ........................... 120 figure 46. write cycle 1 (we# controlled) .......................... 121 figure 47. write cycle 2 (ce#1 or ce2 controlled) ............... 122 figure 48. write cycle 3 (we# controlled, oe# low) ............ 123 figure 49. write cycle 4 (bhe#/ble# controlled, oe# low) .. 123 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 37. truth table ........................................................124 psram type 6 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 functional description . . . . . . . . . . . . . . . . . . . . . 126 absolute maximum ratings . . . . . . . . . . . . . . . . . 126 ac characteristics and operating conditions . 127 ac test conditions . . . . . . . . . . . . . . . . . . . . . . 128 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 129 read timings ...................................................................................................... 129 figure 50. read cycle ....................................................... 129 figure 51. page read cycle (8 words access) ...................... 130 write timings ..................................................................................................... 131 figure 52. write cycle #1 (we# controlled) (see note 8) ..... 131 figure 53. write cycle #2 (ce# controlled) (see note 8) ...... 132 deep power-down timing ............................................................................. 132 figure 54. deep power down timing................................... 132 power-on timing ............................................................................................... 132 figure 55. power-on timing ............................................... 132 provisions of address skew ............................................................................133 figure 56. read ............................................................... 133 figure 57. write ............................................................... 133 psram type 7 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 functional description . . . . . . . . . . . . . . . . . . . . . 135 power down (for 32m, 64m only) . . . . . . . . . . . . 135 power down .......................................................................................................135 power down program sequence ................................................................. 136 address key ....................................................................................................... 136 absolute maximum ratings . . . . . . . . . . . . . . . . . 137 package capacitance . . . . . . . . . . . . . . . . . . . . . . 137 power down parameters ................................................................................ 141 other timing parameters ............................................................................... 141 ac test conditions ......................................................................................... 142 ac measurement output load circuits ................................................... 142 figure 58. ac output load circuit ? 16 mb .......................... 142 figure 59. ac output load circuit ? 32 mb and 64 mb........... 142 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 143 read timings ...................................................................................................... 143 figure 60. read timing #1 (basic timing) ........................... 143 figure 61. read timing #2 (oe# address access................. 143 figure 62. read timing #3 (lb#/ub# byte access) ............. 144 figure 63. read timing #4 (page address access after ce1# control access for 32m and 64m only) ............................... 144 figure 64. read timing #5 (random and page address access for 32m and 64m only) ......................................................... 145 write timings .....................................................................................................145 figure 65. write timing #1 (basic timing) .......................... 145 figure 66. write timing #2 (we# control).......................... 146 figure 67. write timing #3-1(we#/lb#/ub# byte write control) ................................................................. 146 figure 68. write timing #3-3 (we#/lb#/ub# byte write control) ................................................................. 147 figure 69. write timing #3-4 (we#/lb#/ub# byte write control) ................................................................. 147 read/write timings ..........................................................................................148 figure 70. read/write timing #1-1 (ce1# control) ............. 148 figure 71. read / write timing #1-2 (ce1#/we#/oe# control) ................................................ 148 figure 72. read / write timing #2 (oe#, we# control) ....... 149 figure 73. read / write timing #3 (oe#, we#, lb#, ub# control) ........................................ 149 figure 74. power-up timing #1 ......................................... 150 figure 75. power-up timing #2 ......................................... 150 figure 76. power down entry and exit timing ..................... 150 figure 77. standby entry timing after read or write ............ 151 figure 78. power down program timing (for 32m/64m only). 151 sram common features . . . . . . . . . . . . . . . . . . . . . . . . 152 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 functional description . . . . . . . . . . . . . . . . . . . . . 153 4m version f, 4m version g, 8m version c ......................................... 153 byte mode ............................................................................................................ 153 functional description . . . . . . . . . . . . . . . . . . . . . 154 8m version d .................................................................................................154 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 155 recommended dc operating conditions (note 1) .............................. 155 capacitance (f=1mhz, t a =25 c) .................................................................. 155 dc operating characteristics ...................................................................... 155 common .......................................................................................................... 155 dc operating characteristics ......................................................................156 4m version f ..................................................................................................156 dc operating characteristics ......................................................................156 4m version g .................................................................................................156 dc operating characteristics ...................................................................... 157 8m version c ................................................................................................. 157 dc operating characteristics ...................................................................... 157 8m version d ................................................................................................. 157 ac operating conditions . . . . . . . . . . . . . . . . . . 158 test conditions .................................................................................................158 figure 79. ac output load................................................ 158 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 158 read/write characteristics (v cc =2.7-3.3v) .............................................158 data retention characteristics (4m version f) ......................................159 data retention characteristics (4m version g) .....................................160 data retention characteristics (8m version c) .....................................160 data retention characteristics (8m version d) .....................................160 timing diagrams ................................................................................................160 figure 80. timing waveform of read cycle(1) (address controlled, cs#1=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il ) ...... 160 figure 81. timing waveform of read cycle(2) (we#=v ih , if byte#
november 22, 2004 s71pl254/127/064/032j_00_a6 7 advance information is low, ignore ub#/lb# timing) ........................................ 161 figure 82. timing waveform of write cycle(1) (we# controlled, if byte# is low, ignore ub#/lb# timing).............................. 161 figure 83. timing waveform of write cycle(2) (cs# controlled, if byte# is low, ignore ub#/lb# timing).............................. 162 figure 84. timing waveform of write cycle(3) (ub#, lb# controlled) ...................................................................... 162 figure 85. data retention waveform .................................. 163 psram type 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 functional description . . . . . . . . . . . . . . . . . . . . 164 absolute maximum ratings . . . . . . . . . . . . . . . . 164 timing test conditions . . . . . . . . . . . . . . . . . . . 170 output load circuit ......................................................................................... 171 figure 86. output load circuit ........................................... 171 power up sequence . . . . . . . . . . . . . . . . . . . . . . . 171 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 183 read cycle .......................................................................................................... 183 figure 87. timing of read cycle (ce# = oe# = v il , we# = zz# = v ih )................................................................................ 183 figure 88. timing waveform of read cycle (we# = zz# = v ih ) ................................................ 184 figure 89. timing waveform of page mode read cycle (we# = zz# = v ih )............................................................................ 185 write cycle .........................................................................................................186 figure 90. timing waveform of write cycle (we# control, zz# = v ih ) ............................................................................... 186 figure 91. timing waveform of write cycle (ce# control, zz# = v ih ) ............................................................................... 186 figure 92. timing waveform of page mode write cycle (zz# = v ih ) 187 partial array self refresh (par) .................................................................. 188 temperature compensated refresh (for 64mb) ................................... 188 deep sleep mode ............................................................................................. 188 reduced memory size (for 32m and 16m) ................................................ 188 other mode register settings (for 64m) ...................................................189 figure 93. mode register .................................................. 189 figure 94. mode register update timings (ub#, lb#, oe# are don?t care)..................................................................... 190 figure 95. deep sleep mode - entry/exit timings................. 190 revision summary
8 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information mcp block diagram notes: 1. for 1 flash + psram, ce#f1=ce#. for 2 flash + psram, ce#=ce#f1 and ce#f2 is the chip-enable for the second flash. 2. for 256mb only, flash 1 = flash 2 = s29pl127j. v ss reset# flash 1 io 15 -io 0 v cc f dq 15 to dq 0 ry/by# wp#/acc v cc v cc ce#f1 flash-only address shared address oe# we# flash 2 (note 2) ce#f2 (note 1) v ccs v cc ce#s ub#s lb#s ce# ub# lb# psram/sram ce2
november 22, 2004 s71pl254/127/064/032j_00_a6 9 advance information connection diagram (S71PL032J) notes: 1. may be shared depending on density. ? a19 is shared for the 16m psram configuration. ? a18 is shared for the 8m (p)sram and above configurations. 2. connecting all vcc and vss balls to vcc and vss is recommended. mcp flash-only addresses shared addresses S71PL032Ja0 a20 a19-a0 S71PL032J80 a20-a19 a18-a0 S71PL032J08 a20-a19 a18-a0 S71PL032J40 a20-a18 a17-a0 S71PL032J04 a20-a18 a17-a0 c3 ub# d3 a18 e3 a17 f3 dq1 g3 dq9 h3 dq10 dq2 b3 lb# c5 ce2s a20 g5 dq4 h5 vccs rfu b5 we# c6 a19 d6 a9 e6 a10 f6 dq6 g6 dq13 h6 dq12 dq5 b6 a8 c4 rst#f ry/by# g4 dq3 h4 vccf dq11 b4 wp/acc c7 a12 d7 a13 e7 a14 f7 rfu g7 dq15 h7 dq7 dq14 b7 a11 c8 a15 d8 rfu e8 rfu f8 a16 g8 rfu vss c2 a6 d2 a5 e2 a4 f2 vss g2 oe# h2 dq0 ce1#s dq8 b2 a7 c1 a3 d1 a2 e1 a1 f1 a0 g1 ce1#f f5 f4 b1 b8 a3 a5 a6 a4 a7 a2 ram only shared (note 1) flash only legend reserved fo r future use 56-ball fine-pitch ball grid array (top view, balls facing down)
10 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information connection diagram (s71pl064j) notes: 1. may be shared depending on density. ? a20 is shared for the 32m psram configuration. ? a19 is shared for the 16m psram and above configurations. ? a18 is shared for the 8m (p)sram and above configurations. 2. connecting all vcc and vss balls to vcc and vss is recommended. mcp flash-only addresses shared addresses s71pl064jb0 a21 a20-a0 s71pl064ja0 a21-a20 a19-a0 s71pl064j80 a21-a19 a18-a0 s71pl064j08 a21-a19 a18-a0 c3 ub# d3 a18 e3 a17 f3 dq1 g3 dq9 h3 dq10 dq2 b3 lb# c5 ce2s a20 g5 dq4 h5 vccs rfu b5 we# c6 a19 d6 a9 e6 a10 f6 dq6 g6 dq13 h6 dq12 dq5 b6 a8 c4 rst#f ry/by# g4 dq3 h4 vccf dq11 b4 wp/acc c7 a12 d7 a13 e7 a14 f7 rfu g7 dq15 h7 dq7 dq14 b7 a11 c8 a15 d8 a21 e8 rfu f8 a16 g8 rfu vss c2 a6 d2 a5 e2 a4 f2 vss g2 oe# h2 dq0 ce1#s dq8 b2 a7 c1 a3 d1 a2 e1 a1 f1 a0 g1 ce1#f f5 f4 b1 b8 a3 a5 a6 a4 a7 a2 ram only shared (note 1) flash only legend reserved fo r future use 56-ball fine-pitch ball grid array (top view, balls facing down)
november 22, 2004 s71pl254/127/064/032j_00_a6 11 advance information connection diagram (s71pl127j) notes: 1. may be shared depending on density. ? a21 is shared for the 64m psram configuration. ? a20 is shared for the 32m psram and above configurations. 1. a19 is shared for the 16m psram and above configurations. 2. connecting all vcc & vss balls to vcc & vss is recommended. 3. ball l5 will be vccf in the 84-ball density upgrades. do not connect to vss or any other signal. mcp flash-only addresses shared addresses s71pl127jc0 a22 a21-a0 s71pl127jb0 a22-a21 a20-a0 s71pl127ja0 a22-a20 a19-a0 e4 ub# f4 a18 g4 a17 h4 dq1 j4 dq9 k4 dq10 dq2 d 4 e 6 ce2s a20 j6 dq4 k6 vccs rfu d 6 rfu e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 k7 dq12 dq5 d 7 e5 rst#f ry/by# j5 dq3 k5 vccf dq11 d5 rfu e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 k8 dq7 dq14 d8 e 9 f9 a21 g9 a22 h9 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# k3 dq0 ce1#s dq8 d3 e2 f2 a2 g2 a1 h2 a0 j2 ce#f h6 h5 b6 b5 ram only shared (note 1) flash only legend reserved fo r future use rfu rfu* l6 l5 lb# c 4 we# c6 a8 c7 wp/acc c5 a11 c8 a7 c3 a3 d2 a15 d9 a1 nc a10 nc m1 m10 nc nc *see notes below 64-ball fine-pitch ball grid array (top view, balls facing down)
12 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information connection diagram (s71pl254j) notes: 1. may be shared depending on density. ? a21 is shared for the 64m psram configuration. ? a20 is shared for the 32m psram configuration. 2. connecting all vcc & vss balls to vcc & vss is recommended. special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultra- sonic cleaning methods. the package and/ or data integrity may be compromised mcp flash-only addresses shared addresses s71pl254jc0 a22 a21-a0 s71pl254jb0 a22-a21 a20-a0 e4 ub# f4 a18 g4 a17 h4 dq1 j4 dq9 dq10 d 4 e 6 ce2s a20 j6 dq4 vccs d 6 e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 dq12 d7 e5 rst#f ry/by# j5 dq3 vccf d5 e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 dq7 d8 e 9 f9 a21 g9 a22 h9 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# dq0 ce1#s d3 e2 f2 a2 g2 a1 h2 a0 j2 ce#f1 h6 h5 ram only shared (note 1) flash only legend reserved fo r future use a3 d2 a15 d9 a1 nc a10 nc m1 m10 nc nc c 4 lb# we# c7 a8 wp/acc c8 a11 c9 rfu c3 a7 c2 rfu c6 c5 b4 rfu rfu b7 rfu ce#f2 b8 rfu b9 rfu b3 rfu b2 rfu b6 b5 l4 rfu rfu l7 rfu vccf l8 rfu l9 rfu l3 rfu l2 rfu l6 l5 k4 dq2 rfu k7 dq5 dq11 k8 dq14 k9 rfu k3 dq8 k2 rfu k6 k5 rfu rfu h6 h5 rfu rfu h6 h5 2nd flash only 84-ball fine-pitch ball grid array (top view, balls facing down)
november 22, 2004 s71pl254/127/064/032j_00_a6 13 advance information if the package body is exposed to temperatures above 150 c for prolonged peri- ods of time. pin description a21?a0 = 22 address inputs (common) dq15?dq0 = 16 data inputs/outputs (common) ce1#f = chip enable 1 (flash) ce#f2 = chip enable 2 (flash) ce1#ps = chip enable 1 (psram) ce2ps = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output (flash 1) ub# = upper byte control (psram) lb# = lower byte control (psram) reset# = hardware reset pin, active low (flash 1) wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc ps = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 22 16 dq15?dq0 a21?a0 ce1#f oe# we # reset# r y/by# wp#/acc ub# ce2#f ce2ps ce1#ps lb#
14 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information ordering information the order number is formed by a valid combinations of the following: s71pl 127 j b0 ba w 9 z 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number see the valid combinations table. package modifier 0 = 7 x 9mm, 1.2mm height, 56 balls (tlc056 or tsc065) 9 = 8 x 11.6mm, 1.2mm height, 64 balls (tla064 or tsb064) t = 8 x 11.6mm, 1.4mm height, 84 balls (fta084) temperature range w = wireless (-25 c to +85 c) i=industrial (-40 c to +85 c) package type ba = fine-pitch bga lead (pb)-free compliant package bf = fine-pitch bga lead (pb)-free package psram density c0 = 64mb psram b0 = 32mb psram a0 = 16mb psram 80 = 8mb psram 40 = 4mb psram 08 = 8mb sram 04 = 4mb sram process technology j = 110 nm, floating gate technology flash density 254 = 256mb 127 = 128mb 064 = 64mb 032 = 32mb product family s71pl multi-chip product (mcp) 3.0-volt simultaneous read/write, page mode flash memory and ram
november 22, 2004 s71pl254/127/064/032j_00_a6 15 advance information S71PL032J valid combinations speed options (ns) (p)sram type/access time (ns) package marking base ordering part number package & temperature package modifier/ model number packing type S71PL032J04 baw 0b 0, 2, 3 (note 1) 65 sram2 / 70 (note 2) S71PL032J04 0f sram3 / 70 S71PL032J04 0k sram4 / 70 S71PL032J40 0k psram4 / 70 S71PL032J80 0p psram5 / 70 S71PL032J08 0b sram2 / 70 S71PL032J40 07 psram1 / 70 S71PL032J80 07 psram1 / 70 S71PL032Ja0 07 65 psram1 / 70 S71PL032Ja0 0f psram3 / 70 S71PL032Ja0 0z psram2 / 70 S71PL032J04 bfw 0b 0, 2, 3 (note 1) 65 sram2 / 70 (note 2) S71PL032J04 0f sram3 / 70 S71PL032J04 0k sram4 / 70 S71PL032J40 0k psram4 / 70 S71PL032J80 0p psram5 / 70 S71PL032J08 0b sram2 / 70 S71PL032J40 07 psram1 / 70 S71PL032J80 07 psram1 / 70 S71PL032Ja0 07 65 psram1 / 70 S71PL032Ja0 0f psram3 / 70 S71PL032Ja0 0z psram2 / 70 S71PL032J04 bai 0b 0, 2, 3 (note 1) 65 sram2 / 70 (note 2) S71PL032J04 0f sram3 / 70 S71PL032J04 0k sram4 / 70 S71PL032J40 0k psram4 / 70 S71PL032J80 0p psram5 / 70 S71PL032J08 0b sram2 / 70 S71PL032J40 07 psram1 / 70 S71PL032J80 07 psram1 / 70 S71PL032Ja0 07 65 psram1 / 70 S71PL032Ja0 0f psram3 / 70 S71PL032Ja0 0z psram2 / 70 S71PL032J04 bfi 0b 0, 2, 3 (note 1) 65 sram2 / 70 (note 2) S71PL032J04 0f sram3 / 70 S71PL032J04 0k sram4 / 70 S71PL032J40 0k psram4 / 70 S71PL032J80 0p psram5 / 70 S71PL032J08 0b sram2 / 70 S71PL032J40 07 psram1 / 70 S71PL032J80 07 psram1 / 70 S71PL032Ja0 07 65 psram1 / 70 S71PL032Ja0 0f psram3 / 70 S71PL032Ja0 0z psram2 / 70
16 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information s71pl064j valid combinations speed options (ns) (p)sram type/access time (ns) package marking base ordering part number package & temperature package modifier/ model number packing type s71pl064j08 baw 0b 0, 2, 3 (note 1) 65 sram1 / 70 (note 2) s71pl064j08 0u sram3 / 70 s71pl064j80 0k psram1 /70 s71pl064j80 07 psram1 / 70 s71pl064j80 0p psram5 / 70 s71pl064ja0 0z psram7 / 70 s71pl064ja0 0b psram3 / 70 s71pl064ja0 07 psram1 / 70 s71pl064ja0 0p psram7 / 70 s71pl064jb0 07 psram1 / 70 s71pl064jb0 0b psram2 / 70 s71pl064jb0 0u psram6 / 70 s71pl064j08 bfw 0b 0, 2, 3 (note 1) 65 sram1 / 70 (note 2) s71pl064j08 0u sram3 / 70 s71pl064j80 0k psram1 /70 s71pl064j80 07 psram1 / 70 s71pl064j80 0p psram5 / 70 s71pl064ja0 0z psram7 / 70 s71pl064ja0 0b psram3 / 70 s71pl064ja0 07 psram1 / 70 s71pl064ja0 0p psram7 / 70 s71pl064jb0 07 psram1 / 70 s71pl064jb0 0b psram2 / 70 s71pl064jb0 0u psram6 / 70 s71pl064j08 bai 0b 0, 2, 3 (note 1) 65 sram1 / 70 (note 2) s71pl064j08 0u sram3 / 70 s71pl064j80 0k psram1 /70 s71pl064j80 07 psram1 / 70 s71pl064j80 0p psram5 / 70 s71pl064ja0 0z psram7 / 70 s71pl064ja0 0b psram3 / 70 s71pl064ja0 07 psram1 / 70 s71pl064ja0 0p psram7 / 70 s71pl064jb0 07 psram1 / 70 s71pl064jb0 0b psram2 / 70 s71pl064jb0 0u psram6 / 70 notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
november 22, 2004 s71pl254/127/064/032j_00_a6 17 advance information s71pl064j08 bfi 0b 0, 2, 3 (note 1) 65 sram1 / 70 (note 2) s71pl064j08 0u sram3 / 70 s71pl064j80 0k psram1 /70 s71pl064j80 07 psram1 / 70 s71pl064j80 0p psram5 / 70 s71pl064ja0 0z psram7 / 70 s71pl064ja0 0b psram3 / 70 s71pl064ja0 07 psram1 / 70 s71pl064ja0 0p psram7 / 70 s71pl064jb0 07 psram1 / 70 s71pl064jb0 0b psram2 / 70 s71pl064jb0 0u psram6 / 70 s71pl127j valid combinations speed options (ns) (p)sram type/access time (ns) package marking base ordering part number package & temperature package modifier/model number packing type s71pl127ja0 baw 9p 0, 2, 3 (note 1) 65 psram7 / 70 (note 2) s71pl127ja0 9z psram7 / 70 s71pl127ja0 97 psram1 / 70 s71pl127jb0 97 psram1 / 70 s71pl127jb0 9z psram7 / 70 s71pl127jb0 9u psram6 /70 s71pl127jc0 97 psram1 /70 s71pl127jc0 9z psram7 / 70 s71pl127jc0 9u psram6 / 70 s71pl127jb0 9b psram2 / 70 s71pl127ja0 bfw 9p 0, 2, 3 (note 1) 65 psram7 / 70 (note 2) s71pl127ja0 9z psram7 / 70 s71pl127ja0 97 psram1 / 70 s71pl127jb0 97 psram1 / 70 s71pl127jb0 9z psram7 / 70 s71pl127jb0 9u psram6 / 70 s71pl127jc0 97 psram1 /70 s71pl127jc0 9z psram7 / 70 s71pl127jc0 9u psram6 / 70 s71pl127jb0 9b psram2 / 70 s71pl064j valid combinations speed options (ns) (p)sram type/access time (ns) package marking base ordering part number package & temperature package modifier/ model number packing type notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
18 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information s71pl127ja0 bai 9p 0, 2, 3 (note 1) 65 psram7 / 70 (note 2) s71pl127ja0 9z psram7 / 70 s71pl127ja0 97 psram1 / 70 s71pl127jb0 97 psram1 / 70 s71pl127jb0 9z psram7 / 70 s71pl127jb0 9u psram6 / 70 s71pl127jc0 97 psram1 /70 s71pl127jc0 9z psram7 / 70 s71pl127jc0 9u psram6 / 70 s71pl127jb0 9b psram2 / 70 s71pl127ja0 bfi 9p 0, 2, 3 (note 1) 65 psram7 / 70 (note 2) s71pl127ja0 9z psram7 / 70 s71pl127ja0 97 psram1 / 70 s71pl127jb0 97 psram1 / 70 s71pl127jb0 9z psram7 / 70 s71pl127jb0 9u psram6 / 70 s71pl127jb0 9b psram2 / 70 s71pl127jc0 97 psram1 /70 s71pl127jc0 9z psram7 / 70 s71pl127jc0 9u psram6 / 70 s71pl127j valid combinations speed options (ns) (p)sram type/access time (ns) package marking base ordering part number package & temperature package modifier/model number packing type notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
november 22, 2004 s71pl254/127/064/032j_00_a6 19 advance information s71pl254j valid combinations speed options (ns) (p)sram type/access time (ns) package marking base ordering part number package & temperature model number packing type s71pl254jb0 baw t7 0, 2, 3 (note 1) 65 psram1 / 70 (note 2) s71pl254jb0 tb psram2 /70 s71pl254jb0 tu psram6 / 70 s71pl254jc0 tb psram2 / 70 s71pl254jc0 tz psram7 / 70 s71pl254jb0 bfw t7 0, 2, 3 (note 1) 65 psram1 / 70 (note 2) s71pl254jb0 tb psram2 /70 s71pl254jb0 tu psram6 / 70 s71pl254jc0 tb psram2 / 70 s71pl254jc0 tz psram7 / 70 s71pl254jb0 bai t7 0, 2, 3 (note 1) 65 psram1 / 70 (note 2) s71pl254jb0 tb psram2 /70 s71pl254jb0 tu psram6 / 70 s71pl254jc0 tb psram2 / 70 s71pl254jc0 tz psram7 / 70 s71pl254jb0 bfi t7 0, 2, 3 (note 1) 65 psram1 / 70 (note 2) s71pl254jb0 tb psram2 /70 s71pl254jb0 tu psram6 / 70 s71pl254jc0 tb psram2 / 70 s71pl254jc0 tz psram7 / 70 notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
20 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information physical dimensions tlc056?56-ball fine-pitch ball grid array (fbga) 9 x 7mm package 3348 \ 16-038.22a package tlc 056 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 56 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 56x a1 a2 a 0.15 m m c c ab 0.08 pin a1
november 22, 2004 s71pl254/127/064/032j_00_a6 21 advance information tsc056?56-ball fine-pitch ball grid array (fbga) 9 x 7mm package 3427 \ 16-038.22 package tsc 056 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 56 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 56x a1 a2 a 0.15 m m c c ab 0.08 pin a1
22 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information tla064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6mm package 3352 \ 16-038.22a package tla 064 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10, f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.20 c 0.08 c b 64x 6 0.08 m c 0.15 m c a b a2 a a1 side view l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view pin a1 7 10 index mark c 0.15 (2x) (2x) c 0.15 b a d e pin a1 top view corner
november 22, 2004 s71pl254/127/064/032j_00_a6 23 advance information tsb064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3351 \ 16-038.22a package tsb 064 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 017 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10 f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c c 0.08 a1 b 64x 0.15 m c a b 0.08 m c 6 side view 7 se e1 corner pin a1 a c db d1 a 10 ed 9 8 6 5 3 ee 2 4 7 e d 0.15 c (2x) gfe k jh sd 7 m l 1 c c 0.15 b (2x) 0.20 10 pin a1 corner index mark a2 a top view bottom view
24 s71pl254/127/064/032j_00_a6 november 22, 2004 advance information fta084?84-ball fine-pitch ball grid array (fbga) 8 x 11.6mm 3388 \ 16-038.21a package fta 084 jedec n/a d x e 11.60 mm x 8.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.17 --- --- ball height a2 1.02 --- 1.17 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10,e1,e10 f1,f10,g1,g10,h1,h10 j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. (2x) c 0.08 0.20 c c 6 b side view 84x a1 a2 a 0.15 m c mc ab 0.08 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd a e b c 0.15 d c 0.15 (2x) index mark 10 top view corner pin a1
publication number s29pl127j_064j_032j_mcp revision a amendment 3 issue date august 12, 2004 advance information s29pl127j/s29pl064j/s29pl032j for mcp 128/64/32 megabit (8/4/2 m x 16-bit) cmos 3.0 volt-only, simultaneous read/write flash memory with enhanced versatileio tm control distinctive characteristics architectural advantages ? 128/64/32 mbit page mode devices ? page size of 8 words: fast page read access from random locations within the page ? single power supply operation ? full voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency switching from write to read operations ? flexbank architecture (pl127j/pl064j/pl032j) ? 4 separate banks, with up to two simultaneous operations per device ?bank a: pl127j -16 mbit (4 kw x 8 and 32 kw x 31) pl064j - 8 mbit (4 kw x 8 and 32 kw x 15) pl032j - 4 mbit (4 kw x 8 and 32 kw x 7) ?bank b: pl127j - 48 mbit (32 kw x 96) pl064j - 24 mbit (32 kw x 48) pl032j - 12 mbit (32 kw x 24) ?bank c: pl127j - 48 mbit (32 kw x 96) pl064j - 24 mbit (32 kw x 48) pl032j - 12 mbit (32 kw x 24) ?bank d: pl127j -16 mbit (4 kw x 8 and 32 kw x 31) pl064j - 8 mbit (4 kw x 8 and 32 kw x 15) pl032j - 4 mbit (4 kw x 8 and 32 kw x 7) ? enhanced versatilei/o tm (v io ) control ? output voltage generated and input voltages tolerated on all control inputs and i/os is determined by the voltage on the v io pin ?v io options at 1.8 v and 3 v i/o for pl127j devices ?3v v io for pl064j and pl032j devices ? secured silicon sector region ? up to 128 words accessible through a command sequence ? up to 64 factory-locked words ? up to 64 customer-lockable words ? both top and bottom boot blocks in one device ? manufactured on 110 nm process technology ? data retention: 20 years typical ? cycling endurance: 1 million cycles per sector typical performance characteristics ? high performance ? page access times as fast as 20 ns ? random access times as fast as 55 ns ? power consumption (typical values at 10 mhz) ? 45 ma active read current ? 17 ma program/erase current ? 0.2 a typical standby mode current software features ? software command-set compatible with jedec 42.4 standard ? backward compatible with am29f, am29lv, am29dl, and am29pdl families and mbm29qm/rm, mbm29lv, mbm29dl, mbm29pdl families ? cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices ? erase suspend / erase resume ? suspends an erase operation to allow read or program operations in other sectors of same bank ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences
26 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information hardware features ? ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method to reset the device to reading array data ? wp#/ acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 4k word sectors. ?at v ih , allows removal of sector protection ?at v hh , provides accelerated programming in a factory setting ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ? package options ? standard discrete pinouts 11 x 8 mm, 80-ball fine-pitch bga (pl127j) (vbg080) 8 x 6 mm, 48-ball fine pitch bga (pl064j/pl032j) (vbk048) ? mcp-compatible pinout 8 x 11.6 mm, 64-ball fine-pitch bga (pl127j) 7 x 9 mm, 56-ball fine-pitch bga (pl064j and pl032j) compatible with mcp pinout, allowing easy integration of ram into existing designs
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 27 advance information general description the pl127j/pl064j/pl032j is a 128/128/64/32 mbit, 3.0 volt-only page mode and simultaneous read/write flash memory device organized as 8/8/4/2 mwords. the devices are offered in the following packages: ? 11mm x 8mm, 64-ball fine-pitch bga standalone (all) ? 9mm x 8mm, 80-ball fine-pitch bga standalone (pl127j) ? 8mm x 11.6mm, 64-ball fine pitch bga multi-chip compatible (pl127j) the word-wide data (x16) appears on dq15-dq0. this device can be pro - grammed in-system or in standard eprom programmers. a 12.0 v v pp is not required for write or erase operations. the device offers fast page access times of 20 to 30 ns, with corresponding ran - dom access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. simultaneous read/write operation with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into 4 bank s, which can be considered to be four separate memory arrays as far as certain operations are concerned. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediatel y and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from wa iting for the completion of a program or erase operation, greatly improving system performance. the device can be organized in both top and bottom sector configurations. the banks are organized as follows: page mode features the page size is 8 words. after initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires a single 3.0 volt power supply (2.7 v to 3.6 v) for both read and write functions. internally ge nerated and regulated voltages are pro - vided for the program and erase operations. the device is entirely command set compatible with the jedec 42.4 single- power-supply flash standard . commands are written to the command regis - ter using standard microprocessor write timing. register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming bank pl127j sectors pl064j sectors pl032j sectors a 16 mbit (4 kw x 8 and 32 kw x 31) 8 mbit (4 kw x 8 and 32 kw x 15) 4 mbit (4 kw x 8 and 32 kw x 7) b 48 mbit (32 kw x 96) 24 mbit (32 kw x 48) 12 mbit (32 kw x 24) c 48 mbit (32 kw x 96) 24 mbit (32 kw x 48) 12 mbit (32 kw x 24) d 16 mbit (4 kw x 8 and 32 kw x 31) 8 mbit (4 kw x 8 and 32 kw x 15) 4 mbit (4 kw x 8 and 32 kw x 7)
28 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or ac - cept another command. the sector erase architecture allows memory sectors to be erased and repro - grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automat - ically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combina - tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true backgrou nd erase can thus be achieved. if a read is needed from the secured silicon sector area (one time program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device in to the standby mode. power consumption is greatly reduced in both these modes. the device electrically erases all bits within a sector simultaneously via fowler- nordheim tunneling. the data is programmed using hot electron injection.
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 29 advance information product selector guide note: contact factory for availability. part number s29pl032j/s29pl064j/s29pl127j speed option v cc ,v io = 2.7?3.6 v 55 (note) 60 70 v cc = 2.7?3.6 v, v io = 1.65?1.95 v (pl127j only) 65 70 max access time, ns (t acc ) 55 (note) 60 65 70 70 max ce# access, ns (t ce ) max page access, ns (t pacc ) 20 (note) 25 30 30 30 max oe# access, ns (t oe )
30 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information block diagram notes: 1. ry/by# is an open drain output. 2. amax = a22 (pl127j), a21 (pl064j), a20 (pl032j) v cc v ss state control command register pgm voltage generator v cc detector timer erase voltage generator input/output buffers sector switches chip enable output enable logic y-gating cell matrix address latch y-decoder x-decoder data latch reset# ry/by# (see note) amax?a3 a2?a0 ce# we# dq15?dq0 v io oe#
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 31 advance information simultaneous read/write block diagram note: amax = a22 (pl127j), a21 (pl064j), a20 (pl032j) note: pinout shown for pl127j. v cc v ss bank a address bank b address amax?a0 reset# we# ce# dq0?dq15 state control & command register ry/by# bank a x-decoder oe# dq15?dq0 status control amax?a0 amax?a0 a22?a0 a22?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank b x-decoder y-gate bank c x-decoder bank d x-decoder y-gate bank c address bank d address wp#/acc
32 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information pin description amax?a0 = address bus dq15?dq0 = 16-bit data inputs/outputs/float ce# = chip enable inputs oe# = output enable input we# = write enable v ss = device ground nc = pin not connected internally ry/by# = ready/busy output and open drain. when ry/by#= v ih , the device is ready to accept read operations and commands. when ry/by#= v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation. wp#/acc = write protect/acceleration input. when wp#/acc= v il , the highest and lowest two 4k-word sectors are write protected regardless of other sector protection configurations. when wp#/ acc= v ih , these sector are unprotected unless the dyb or ppb is programmed. when wp#/acc= 12v, program and erase operations are accelerated. v io = input/output buffer power supply (1.65 v to 1.95 v (for pl127j) or 2.7 v to 3.6 v (for all plxxxj devices) v cc = chip power supply (2.7 v to 3.6 v or 2.7 to 3.3 v) reset# = hardware reset pin ce#1 = chip enable inputs notes: 1. amax = a22 (pl127j), a21 (pl064j), a20 (pl032j) logic symbol max+1 16 dq15?dq0 amax?a0 ce# oe# we# reset# ry/by# wp#/acc v io (v ccq )
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 33 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. tab l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend: l= logic low = v il , h = logic high = v ih , v id = 11.5-12.5 v, v hh = 8.5-9.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the high voltage sector protection section. 2. wp#/acc must be high when writing to upper two and lower two sectors. requirements for reading array data to read array data from the outputs, the system must drive the oe# and appro - priate ce# pins. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. refer to ta b l e 23 for timing specifications and to figure 11 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. random read (non-page read) address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad - dresses and stable ce# to valid data at the output inputs. the output enable ta b l e 1 . pl127j device bus operations operation ce# oe# we# reset# wp#/acc addresses (amax?a0) dq15? dq0 read l l h h x a in d out write l h l h x (note 2 ) a in d in standby v io 0.3 v x x v io 0.3 v x (note 2 ) x high-z output disable l h h h x x high-z reset x x x l x x high-z temporary sector unprotect (high voltage) x x x v id x a in d in
34 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information access time is the delay from the falling edge of the oe# to valid data at the out - put inputs (assuming the addresses have been stable for at least t acc ?t oe time). page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. address bits amax?a3 select an 8 word page, and address bits a2?a0 select a specific word within that page. this is an asyn - chronous operation with the microprocessor supplying the specific word location. the random or initial page access is t acc or t ce and subsequent page read ac - cesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . fast page mode accesses are obtained by keeping amax?a3 constant and changing a2?a0 to select the specific word within that page. simultaneous read/write operation in addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). the bank can be selected by bank addresses (pl127j: a22?a20, l064j: a21?a19, pl032j: a20?a18) with zero latency. the simultaneous operation can execute multi-function mode in the same bank. ta b l e 2 . page select word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1 ta b l e 3 . bank select bank pl127j: a22?a20 pl064j: a21?a19 pl032j: a20?a18 bank a 000 bank b 001, 010, 011 bank c 100, 101, 110 bank d 111
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 35 advance information writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once a bank enters the unlock bypass mode, only two write cycles are required to program a word, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 4 indicates the set of address space that each sector occupies. a ?bank ad - dress? is the set of address bits required to uniquely select a bank. similarly, a ?sector address? refers to the address bits required to uniquely select a sector. the ?command definitions? section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. i cc2 in the dc characteristics table represents the active current specification for the write mode. see the timing specification tables and timing diagrams in the reset for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the afore - mentioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin re - turns the device to normal operation. note that v hh must not be asserted on wp#/acc for operations other than acce lerated programming, or device damage may result. in addition, the wp#/acc pin should be raised to v cc when not in use. that is, the wp#/acc pin should not be left floating or unconnected; incon - sistent behavior of the device may result. autoselect functions if the system writes the autoselect co mmand sequence, the device enters the au - toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to the secured silicon sector ad - dresses and autoselect command sequence for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device
36 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac - tive current until the operation is completed. i cc3 in ?dc characteristics? represents the cmos standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the de - vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# con - trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. note that during automa tic sleep mode, oe# must be at v ih before the device reduces current to the stated sleep mode specification. i cc5 in ?dc characteristics? represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driv en low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal st ate machine to reading array data. the op - eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current ( i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm - ware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin re - mains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/ by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristic tables for reset# parameters and to 13 for the timing diagoutput disable mode when the oe# input is at v ih , output from the device is disabled. the output pins (except for ry/by#) are placed in the highest impedance state.
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 37 advance information ta b l e 4 . pl127j sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 00000000000 4 000000h?000fffh sa1 00000000001 4 001000h?001fffh sa2 00000000010 4 002000h?002fffh sa3 00000000011 4 003000h?003fffh sa4 00000000100 4 004000h?004fffh sa5 00000000101 4 005000h?005fffh sa6 00000000110 4 006000h?006fffh sa7 00000000111 4 007000h?007fffh sa8 00000001xxx 32 008000h?00ffffh sa9 00000010xxx 32 010000h?017fffh sa10 00000011xxx 32 018000h?01ffffh sa11 00000100xxx 32 020000h?027fffh sa12 00000101xxx 32 028000h?02ffffh sa13 00000110xxx 32 030000h?037fffh sa14 00000111xxx 32 038000h?03ffffh sa15 00001000xxx 32 040000h?047fffh sa16 00001001xxx 32 048000h?04ffffh sa17 00001010xxx 32 050000h?057fffh sa18 00001011xxx 32 058000h?05ffffh sa19 00001100xxx 32 060000h?067fffh sa20 00001101xxx 32 068000h?06ffffh sa21 00001110xxx 32 070000h?077fffh sa22 00001111xxx 32 078000h?07ffffh sa23 00010000xxx 32 080000h?087fffh sa24 00010001xxx 32 088000h?08ffffh sa25 00010010xxx 32 090000h?097fffh sa26 00010011xxx 32 098000h?09ffffh sa27 00010100xxx 32 0a0000h ?0a7fffh sa28 00010101xxx 32 0a8000h?0affffh sa29 00010110xxx 32 0b0000h?0b7fffh sa30 00010111xxx 32 0b8000h?0bffffh sa31 00011000xxx 32 0c0000h?0c7fffh sa32 00011001xxx 32 0c8000h?0cffffh sa33 00011010xxx 32 0d0000h ?0d7fffh sa34 00011011xxx 32 0d8000h?0dffffh sa35 00011100xxx 32 0e0000h?0e7fffh sa36 00011101xxx 32 0e8000h?0effffh sa37 00011110xxx 32 0f0000h?0f7fffh sa38 00011111xxx 32 0f8000h?0fffffh
38 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information bank b sa39 00100000xxx 32 100000h?107fffh sa40 00100001xxx 32 108000h?10ffffh sa41 00100010xxx 32 110000h?117fffh sa42 00100011xxx 32 118000h?11ffffh sa43 00100100xxx 32 120000h?127fffh sa44 00100101xxx 32 128000h?12ffffh sa45 00100110xxx 32 130000h?137fffh sa46 00100111xxx 32 138000h?13ffffh sa47 00101000xxx 32 140000h?147fffh sa48 00101001xxx 32 148000h?14ffffh sa49 00101010xxx 32 150000h?157fffh sa50 00101011xxx 32 158000h?15ffffh sa51 00101100xxx 32 160000h?167fffh sa52 00101101xxx 32 168000h?16ffffh sa53 00101110xxx 32 170000h?177fffh sa54 00101111xxx 32 178000h?17ffffh sa55 00110000xxx 32 180000h?187fffh sa56 00110001xxx 32 188000h?18ffffh sa57 00110010xxx 32 190000h?197fffh sa58 00110011xxx 32 198000h?19ffffh sa59 00110100xxx 32 1a0000h ?1a7fffh sa60 00110101xxx 32 1a8000h?1affffh sa61 00110110xxx 32 1b0000h?1b7fffh sa62 00110111xxx 32 1b8000h?1bffffh sa63 00111000xxx 32 1c0000h?1c7fffh sa64 00111001xxx 32 1c8000h?1cffffh sa65 00111010xxx 32 1d0000h ?1d7fffh sa66 00111011xxx 32 1d8000h?1dffffh sa67 00111100xxx 32 1e0000h?1e7fffh sa68 00111101xxx 32 1e8000h?1effffh sa69 00111110xxx 32 1f0000h?1f7fffh sa70 00111111xxx 32 1f8000h?1fffffh sa71 01000000xxx 32 200000h?207fffh sa72 01000001xxx 32 208000h?20ffffh sa73 01000010xxx 32 210000h?217fffh sa74 01000011xxx 32 218000h?21ffffh sa75 01000100xxx 32 220000h?227fffh sa76 01000101xxx 32 228000h?22ffffh sa77 01000110xxx 32 230000h?237fffh sa78 01000111xxx 32 238000h?23ffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 39 advance information bank b sa79 01001000xxx 32 240000h?247fffh sa80 01001001xxx 32 248000h?24ffffh sa81 01001010xxx 32 250000h?257fffh sa82 01001011xxx 32 258000h?25ffffh sa83 01001100xxx 32 260000h?267fffh sa84 01001101xxx 32 268000h?26ffffh sa85 01001110xxx 32 270000h?277fffh sa86 01001111xxx 32 278000h?27ffffh sa87 01010000xxx 32 280000h?287fffh sa88 01010001xxx 32 288000h?28ffffh sa89 01010010xxx 32 290000h?297fffh sa90 01010011xxx 32 298000h?29ffffh sa91 01010100xxx 32 2a0000h ?2a7fffh sa92 01010101xxx 32 2a8000h?2affffh sa93 01010110xxx 32 2b0000h?2b7fffh sa94 01010111xxx 32 2b8000h?2bffffh sa95 01011000xxx 32 2c0000h?2c7fffh sa96 01011001xxx 32 2c8000h?2cffffh sa97 01011010xxx 32 2d0000h ?2d7fffh sa98 01011011xxx 32 2d8000h?2dffffh sa99 01011100xxx 32 2e0000h?2e7fffh sa100 01011101xxx 32 2e8000h?2effffh sa101 01011110xxx 32 2f0000h?2f7fffh sa102 01011111xxx 32 2f8000h?2fffffh sa103 01100000xxx 32 300000h?307fffh sa104 01100001xxx 32 308000h?30ffffh sa105 01100010xxx 32 310000h?317fffh sa106 01100011xxx 32 318000h?31ffffh sa107 01100100xxx 32 320000h?327fffh sa108 01100101xxx 32 328000h?32ffffh sa109 01100110xxx 32 330000h?337fffh sa110 01100111xxx 32 338000h?33ffffh sa111 01101000xxx 32 340000h?347fffh sa112 01101001xxx 32 348000h?34ffffh sa113 01101010xxx 32 350000h?357fffh sa114 01101011xxx 32 358000h?35ffffh sa115 01101100xxx 32 360000h?367fffh sa116 01101101xxx 32 368000h?36ffffh sa117 01101110xxx 32 370000h?377fffh sa118 01101111xxx 32 378000h?37ffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
40 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information bank b sa119 01110000xxx 32 380000h?387fffh sa120 01110001xxx 32 388000h?38ffffh sa121 01110010xxx 32 390000h?397fffh sa122 01110011xxx 32 398000h?39ffffh sa123 01110100xxx 32 3a0000h ?3a7fffh sa124 01110101xxx 32 3a8000h?3affffh sa125 01110110xxx 32 3b0000h?3b7fffh sa126 01110111xxx 32 3b8000h?3bffffh sa127 01111000xxx 32 3c0000h?3c7fffh sa128 01111001xxx 32 3c8000h?3cffffh sa129 01111010xxx 32 3d0000h ?3d7fffh sa130 01111011xxx 32 3d8000h?3dffffh sa131 01111100xxx 32 3e0000h?3e7fffh sa132 01111101xxx 32 3e8000h?3effffh sa133 01111110xxx 32 3f0000h?3f7fffh sa134 01111111xxx 32 3f8000h?3fffffh bank c sa135 10000000xxx 32 400000h?407fffh sa136 10000001xxx 32 408000h?40ffffh sa137 10000010xxx 32 410000h?417fffh sa138 10000011xxx 32 418000h?41ffffh sa139 10000100xxx 32 420000h?427fffh sa140 10000101xxx 32 428000h?42ffffh sa141 10000110xxx 32 430000h?437fffh sa142 10000111xxx 32 438000h?43ffffh sa143 10001000xxx 32 440000h?447fffh sa144 10001001xxx 32 448000h?44ffffh sa145 10001010xxx 32 450000h?457fffh sa146 10001011xxx 32 458000h?45ffffh sa147 10001100xxx 32 460000h?467fffh sa148 10001101xxx 32 468000h?46ffffh sa149 10001110xxx 32 470000h?477fffh sa150 10001111xxx 32 478000h?47ffffh sa151 10010000xxx 32 480000h?487fffh sa152 10010001xxx 32 488000h?48ffffh sa153 10010010xxx 32 490000h?497fffh sa154 10010011xxx 32 498000h?49ffffh sa155 10010100xxx 32 4a0000h ?4a7fffh sa156 10010101xxx 32 4a8000h?4affffh sa157 10010110xxx 32 4b0000h?4b7fffh sa158 10010111xxx 32 4b8000h?4bffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 41 advance information bank c sa159 10011000xxx 32 4c0000h?4c7fffh sa160 10011001xxx 32 4c8000h?4cffffh sa161 10011010xxx 32 4d0000h ?4d7fffh sa162 10011011xxx 32 4d8000h?4dffffh sa163 10011100xxx 32 4e0000h?4e7fffh sa164 10011101xxx 32 4e8000h?4effffh sa165 10011110xxx 32 4f0000h?4f7fffh sa166 10011111xxx 32 4f8000h?4fffffh sa167 10100000xxx 32 500000h?507fffh sa168 10100001xxx 32 508000h?50ffffh sa169 10100010xxx 32 510000h?517fffh sa170 10100011xxx 32 518000h?51ffffh sa171 10100100xxx 32 520000h?527fffh sa172 10100101xxx 32 528000h?52ffffh sa173 10100110xxx 32 530000h?537fffh sa174 10100111xxx 32 538000h?53ffffh sa175 10101000xxx 32 540000h?547fffh sa176 10101001xxx 32 548000h?54ffffh sa177 10101010xxx 32 550000h?557fffh sa178 10101011xxx 32 558000h?15ffffh sa179 10101100xxx 32 560000h?567fffh sa180 10101101xxx 32 568000h?56ffffh sa181 10101110xxx 32 570000h?577fffh sa182 10101111xxx 32 578000h?57ffffh sa183 10110000xxx 32 580000h?587fffh sa184 10110001xxx 32 588000h?58ffffh sa185 10110010xxx 32 590000h?597fffh sa186 10110011xxx 32 598000h?59ffffh sa187 10110100xxx 32 5a0000h ?5a7fffh sa188 10110101xxx 32 5a8000h?5affffh sa189 10110110xxx 32 5b0000h?5b7fffh sa190 10110111xxx 32 5b8000h?5bffffh sa191 10111000xxx 32 5c0000h?5c7fffh sa192 10111001xxx 32 5c8000h?5cffffh sa193 10111010xxx 32 5d0000h ?5d7fffh sa194 10111011xxx 32 5d8000h?5dffffh sa195 10111100xxx 32 5e0000h?5e7fffh sa196 10111101xxx 32 5e8000h?5effffh sa197 10111110xxx 32 5f0000h?5f7fffh sa198 10111111xxx 32 5f8000h?5fffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
42 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information bank c sa199 11000000xxx 32 600000h?607fffh sa200 11000001xxx 32 608000h?60ffffh sa201 11000010xxx 32 610000h?617fffh sa202 11000011xxx 32 618000h?61ffffh sa203 11000100xxx 32 620000h?627fffh sa204 11000101xxx 32 628000h?62ffffh sa205 11000110xxx 32 630000h?637fffh sa206 11000111xxx 32 638000h?63ffffh sa207 11001000xxx 32 640000h?647fffh sa208 11001001xxx 32 648000h?64ffffh sa209 11001010xxx 32 650000h?657fffh sa210 11001011xxx 32 658000h?65ffffh sa211 11001100xxx 32 660000h?667fffh sa212 11001101xxx 32 668000h?66ffffh sa213 11001110xxx 32 670000h?677fffh sa214 11001111xxx 32 678000h?67ffffh sa215 11010000xxx 32 680000h?687fffh sa216 11010001xxx 32 688000h?68ffffh sa217 11010010xxx 32 690000h?697fffh sa218 11010011xxx 32 698000h?69ffffh sa219 11010100xxx 32 6a0000h ?6a7fffh sa220 11010101xxx 32 6a8000h?6affffh sa221 11010110xxx 32 6b0000h?6b7fffh sa222 11010111xxx 32 6b8000h?6bffffh sa223 11011000xxx 32 6c0000h?6c7fffh sa224 11011001xxx 32 6c8000h?6cffffh sa225 11011010xxx 32 6d0000h ?6d7fffh sa226 11011011xxx 32 6d8000h?6dffffh sa227 11011100xxx 32 6e0000h?6e7fffh sa228 11011101xxx 32 6e8000h?6effffh sa229 11011110xxx 32 6f0000h?6f7fffh sa230 11011111xxx 32 6f8000h?6fffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 43 advance information bank d sa231 11100000xxx 32 700000h?707fffh sa232 11100001xxx 32 708000h?70ffffh sa233 11100010xxx 32 710000h?717fffh sa234 11100011xxx 32 718000h?71ffffh sa235 11100100xxx 32 720000h?727fffh sa236 11100101xxx 32 728000h?72ffffh sa237 11100110xxx 32 730000h?737fffh sa238 11100111xxx 32 738000h?73ffffh sa239 11101000xxx 32 740000h?747fffh sa240 11101001xxx 32 748000h?74ffffh sa241 11101010xxx 32 750000h?757fffh sa242 11101011xxx 32 758000h?75ffffh sa243 11101100xxx 32 760000h?767fffh sa244 11101101xxx 32 768000h?76ffffh sa245 11101110xxx 32 770000h?777fffh sa246 11101111xxx 32 778000h?77ffffh sa247 11110000xxx 32 780000h?787fffh sa248 11110001xxx 32 788000h?78ffffh sa249 11110010xxx 32 790000h?797fffh sa250 11110011xxx 32 798000h?79ffffh sa251 11110100xxx 32 7a0000h ?7a7fffh sa252 11110101xxx 32 7a8000h?7affffh sa253 11110110xxx 32 7b0000h?7b7fffh sa254 11110111xxx 32 7b8000h?7bffffh sa255 11111000xxx 32 7c0000h?7c7fffh sa256 11111001xxx 32 7c8000h?7cffffh sa257 11111010xxx 32 7d0000h ?7d7fffh sa258 11111011xxx 32 7d8000h?7dffffh sa259 11111100xxx 32 7e0000h?7e7fffh sa260 11111101xxx 32 7e8000h?7effffh sa261 11111110xxx 32 7f0000h?7f7fffh sa262 11111111000 4 7f8000h?7f8fffh sa263 11111111001 4 7f9000h?7f9fffh sa264 11111111010 4 7fa000h ?7fafffh sa265 11111111011 4 7fb000h?7fbfffh sa266 11111111100 4 7fc000h?7fcfffh sa267 11111111101 4 7fd000h?7fdfffh sa268 11111111110 4 7fe000h?7fefffh sa269 11111111111 4 7ff000h?7fffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
44 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information ta b l e 5 . pl064j sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 0000000000 4 000000h?000fffh sa1 0000000001 4 001000h?001fffh sa2 0000000010 4 002000h?002fffh sa3 0000000011 4 003000h?003fffh sa4 0000000100 4 004000h?004fffh sa5 0000000101 4 005000h?005fffh sa6 0000000110 4 006000h?006fffh sa7 0000000111 4 007000h?007fffh sa8 0000001xxx 32 008000h?00ffffh sa9 0000010xxx 32 010000h?017fffh sa10 0000011xxx 32 018000h?01ffffh sa11 0000100xxx 32 020000h?027fffh sa12 0000101xxx 32 028000h?02ffffh sa13 0000110xxx 32 030000h?037fffh sa14 0000111xxx 32 038000h?03ffffh sa15 0001000xxx 32 040000h?047fffh sa16 0001001xxx 32 048000h?04ffffh sa17 0001010xxx 32 050000h?057fffh sa18 0001011xxx 32 058000h?05ffffh sa19 0001100xxx 32 060000h?067fffh sa20 0001101xxx 32 068000h?06ffffh sa21 0001110xxx 32 070000h?077fffh sa22 0001111xxx 32 078000h?07ffffh bank b sa23 0010000xxx 32 080000h?087fffh sa24 0010001xxx 32 088000h?08ffffh sa25 0010010xxx 32 090000h?097fffh sa26 0010011xxx 32 098000h?09ffffh sa27 0010100xxx 32 0a0000h ?0a7fffh sa28 0010101xxx 32 0a8000h?0affffh sa29 0010110xxx 32 0b0000h?0b7fffh sa30 0010111xxx 32 0b8000h?0bffffh sa31 0011000xxx 32 0c0000h?0c7fffh sa32 0011001xxx 32 0c8000h?0cffffh sa33 0011010xxx 32 0d0000h ?0d7fffh sa34 0011011xxx 32 0d8000h?0dffffh sa35 0011100xxx 32 0e0000h?0e7fffh sa36 0011101xxx 32 0e8000h?0effffh sa37 0011110xxx 32 0f0000h?0f7fffh sa38 0011111xxx 32 0f8000h?0fffffh sa39 0100000xxx 32 100000h?107fffh sa40 0100001xxx 32 108000h?10ffffh sa41 0100010xxx 32 110000h?117fffh sa42 0100011xxx 32 118000h?11ffffh sa43 0100100xxx 32 120000h?127fffh sa44 0100101xxx 32 128000h?12ffffh sa45 0100110xxx 32 130000h?137fffh sa46 0100111xxx 32 138000h?13ffffh sa47 0101000xxx 32 140000h?147fffh
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 45 advance information bank b sa48 0101001xxx 32 148000h?14ffffh sa49 0101010xxx 32 150000h?157fffh sa50 0101011xxx 32 158000h?15ffffh sa51 0101100xxx 32 160000h?167fffh sa52 0101101xxx 32 168000h?16ffffh sa53 0101110xxx 32 170000h?177fffh sa54 0101111xxx 32 178000h?17ffffh sa55 0110000xxx 32 180000h?187fffh sa56 0110001xxx 32 188000h?18ffffh sa57 0110010xxx 32 190000h?197fffh sa58 0110011xxx 32 198000h?19ffffh sa59 0110100xxx 32 1a0000h ?1a7fffh sa60 0110101xxx 32 1a8000h?1affffh sa61 0110110xxx 32 1b0000h?1b7fffh sa62 0110111xxx 32 1b8000h?1bffffh sa63 0111000xxx 32 1c0000h?1c7fffh sa64 0111001xxx 32 1c8000h?1cffffh sa65 0111010xxx 32 1d0000h ?1d7fffh sa66 0111011xxx 32 1d8000h?1dffffh sa67 0111100xxx 32 1e0000h?1e7fffh sa68 0111101xxx 32 1e8000h?1effffh sa69 0111110xxx 32 1f0000h?1f7fffh sa70 0111111xxx 32 1f8000h?1fffffh bank c sa71 1000000xxx 32 200000h?207fffh sa72 1000001xxx 32 208000h?20ffffh sa73 1000010xxx 32 210000h?217fffh sa74 1000011xxx 32 218000h?21ffffh sa75 1000100xxx 32 220000h?227fffh sa76 1000101xxx 32 228000h?22ffffh sa77 1000110xxx 32 230000h?237fffh sa78 1000111xxx 32 238000h?23ffffh sa79 1001000xxx 32 240000h?247fffh sa80 1001001xxx 32 248000h?24ffffh sa81 1001010xxx 32 250000h?257fffh sa82 1001011xxx 32 258000h?25ffffh sa83 1001100xxx 32 260000h?267fffh sa84 1001101xxx 32 268000h?26ffffh sa85 1001110xxx 32 270000h?277fffh sa86 1001111xxx 32 278000h?27ffffh bank c sa87 1010000xxx 32 280000h?287fffh sa88 1010001xxx 32 288000h?28ffffh sa89 1010010xxx 32 290000h?297fffh sa90 1010011xxx 32 298000h?29ffffh sa91 1010100xxx 32 2a0000h ?2a7fffh sa92 1010101xxx 32 2a8000h?2affffh sa93 1010110xxx 32 2b0000h?2b7fffh sa94 1010111xxx 32 2b8000h?2bffffh sa95 1011000xxx 32 2c0000h?2c7fffh table 5. pl064j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
46 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information bank c sa96 1011001xxx 32 2c8000h?2cffffh sa97 1011010xxx 32 2d0000h ?2d7fffh sa98 1011011xxx 32 2d8000h?2dffffh sa99 1011100xxx 32 2e0000h?2e7fffh sa100 1011101xxx 32 2e8000h?2effffh sa101 1011110xxx 32 2f0000h?2f7fffh sa102 1011111xxx 32 2f8000h?2fffffh sa103 1100000xxx 32 300000h?307fffh sa104 1100001xxx 32 308000h?30ffffh sa105 1100010xxx 32 310000h?317fffh sa106 1100011xxx 32 318000h?31ffffh sa107 1100100xxx 32 320000h?327fffh sa108 1100101xxx 32 328000h?32ffffh sa109 1100110xxx 32 330000h?337fffh sa110 1100111xxx 32 338000h?33ffffh sa111 1101000xxx 32 340000h?347fffh sa112 1101001xxx 32 348000h?34ffffh sa113 1101010xxx 32 350000h?357fffh sa114 1101011xxx 32 358000h?35ffffh sa115 1101100xxx 32 360000h?367fffh sa116 1101101xxx 32 368000h?36ffffh sa117 1101110xxx 32 370000h?377fffh sa118 1101111xxx 32 378000h?37ffffh bank d sa119 1110000xxx 32 380000h?387fffh sa120 1110001xxx 32 388000h?38ffffh sa121 1110010xxx 32 390000h?397fffh sa122 1110011xxx 32 398000h?39ffffh sa123 1110100xxx 32 3a0000h ?3a7fffh sa124 1110101xxx 32 3a8000h?3affffh sa125 1110110xxx 32 3b0000h?3b7fffh sa126 1110111xxx 32 3b8000h?3bffffh sa127 1111000xxx 32 3c0000h?3c7fffh sa128 1111001xxx 32 3c8000h?3cffffh sa129 1111010xxx 32 3d0000h ?3d7fffh sa130 1111011xxx 32 3d8000h?3dffffh sa131 1111100xxx 32 3e0000h?3e7fffh sa132 1111101xxx 32 3e8000h?3effffh sa133 1111110xxx 32 3f0000h?3f7fffh sa134 1111111000 4 3f8000h?3f8fffh sa135 1111111001 4 3f9000h?3f9fffh sa136 1111111010 4 3fa000h ?3fafffh sa137 1111111011 4 3fb000h?3fbfffh sa138 1111111100 4 3fc000h?3fcfffh sa139 1111111101 4 3fd000h?3fdfffh sa140 1111111110 4 3fe000h?3fefffh sa141 1111111111 4 3ff000h?3fffffh table 5. pl064j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 47 advance information ta b l e 6 . pl032j sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 000000000 4 000000h?000fffh sa1 000000001 4 001000h?001fffh sa2 000000010 4 002000h?002fffh sa3 000000011 4 003000h?003fffh sa4 000000100 4 004000h?004fffh sa5 000000101 4 005000h?005fffh sa6 000000110 4 006000h?006fffh sa7 000000111 4 007000h?007fffh sa8 000001xxx 32 008000h?00ffffh sa9 000010xxx 32 010000h?017fffh sa10 000011xxx 32 018000h?01ffffh sa11 000100xxx 32 020000h?027fffh sa12 000101xxx 32 028000h?02ffffh sa13 000110xxx 32 030000h?037fffh sa14 000111xxx 32 038000h?03ffffh bank b sa15 001000xxx 32 040000h?047fffh sa16 001001xxx 32 048000h?04ffffh sa17 001010xxx 32 050000h?057fffh sa18 001011xxx 32 058000h?05ffffh sa19 001100xxx 32 060000h?067fffh sa20 001101xxx 32 068000h?06ffffh sa21 001110xxx 32 070000h?077fffh sa22 001111xxx 32 078000h?07ffffh sa23 010000xxx 32 080000h?087fffh sa24 010001xxx 32 088000h?08ffffh sa25 010010xxx 32 090000h?097fffh sa26 010011xxx 32 098000h?09ffffh sa27 010100xxx 32 0a0000h ?0a7fffh sa28 010101xxx 32 0a8000h?0affffh sa29 010110xxx 32 0b0000h?0b7fffh sa30 010111xxx 32 0b8000h?0bffffh sa31 011000xxx 32 0c0000h?0c7fffh sa32 011001xxx 32 0c8000h?0cffffh sa33 011010xxx 32 0d0000h ?0d7fffh sa34 011011xxx 32 0d8000h?0dffffh sa35 011100xxx 32 0e0000h?0e7fffh sa36 011101xxx 32 0e8000h?0effffh sa37 011110xxx 32 0f0000h?0f7fffh sa38 011111xxx 32 0f8000h?0fffffh
48 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information bank c sa39 100000xxx 32 100000h?107fffh sa40 100001xxx 32 108000h?10ffffh sa41 100010xxx 32 110000h?117fffh sa42 100011xxx 32 118000h?11ffffh sa43 100100xxx 32 120000h?127fffh sa44 100101xxx 32 128000h?12ffffh sa45 100110xxx 32 130000h?137fffh sa46 100111xxx 32 138000h?13ffffh sa47 101000xxx 32 140000h?147fffh sa48 101001xxx 32 148000h?14ffffh sa49 101010xxx 32 150000h?157fffh sa50 101011xxx 32 158000h?15ffffh sa51 101100xxx 32 160000h?167fffh sa52 101101xxx 32 168000h?16ffffh sa53 101110xxx 32 170000h?177fffh sa54 101111xxx 32 178000h?17ffffh sa55 110000xxx 32 180000h?187fffh sa56 110001xxx 32 188000h?18ffffh sa57 110010xxx 32 190000h?197fffh sa58 110011xxx 32 198000h?19ffffh sa59 110100xxx 32 1a0000h ?1a7fffh sa60 110101xxx 32 1a8000h?1affffh sa61 110110xxx 32 1b0000h?1b7fffh sa62 110111xxx 32 1b8000h?1bffffh bank d sa63 111000xxx 32 1c0000h?1c7fffh sa64 111001xxx 32 1c8000h?1cffffh sa65 111010xxx 32 1d0000h ?1d7fffh sa66 111011xxx 32 1d8000h?1dffffh sa67 111100xxx 32 1e0000h?1e7fffh sa68 111101xxx 32 1e8000h?1effffh sa69 111110xxx 32 1f0000h?1f7fffh sa70 111111000 4 1f8000h?1f8fffh sa71 111111001 4 1f9000h?1f9fffh sa72 111111010 4 1fa000h ?1fafffh sa73 111111011 4 1fb000h?1fbfffh sa74 111111100 4 1fc000h?1fcfffh sa75 111111101 4 1fd000h?1fdfffh sa76 111111110 4 1fe000h?1fefffh sa77 111111111 4 1ff000h?1fffffh ta b l e 7 . secured silicon sector addresses sector size address range factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh table 6. pl032j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 49 advance information autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming eq uipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on ad - dress pin a9. address pins must be as shown in ta b l e 8 and tab le 11 . in addition, when verifying sector protection, the sector address must appear on the appro - priate highest order address bits (see ta b l e 3 ). ta b l e 8 and ta b l e 11 show the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding iden - tifier code on dq7?dq0. however, the au toselect codes can also be accessed in- system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in ta b l e 17 . note that if a bank address (ba) (on address bits pl127j: a22 ? a20, pl064j: a21 ? a19, pl032j: a20 ?a18) is as - serted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. to access the autoselect codes in-system, the host system can issue the autose - lect command via the command register, as shown in ta b l e 17 . this method does not require v id . refer to the autoselect command sequence for more information. legend: l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = don?t care. note: the autoselect codes may also be acce ssed in-system via command sequences ta b l e 8 . autoselect codes (high voltage method) description ce# oe# we# amax to a12 a1 0 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : spansion products l l h ba x v id x l l x l l l l 0001h device id read cycle 1 l l h ba x v id x l l l l l l h 227eh read cycle 2 l h h h l 2220h (pl127j) 2202h (pl064j) 220ah (pl032j) read cycle 3 l h h h h 2200h (pl127j) 2201h (pl064j) 2201h (pl032j) sector protection verification l l h sa x v id x l l l l l h l 0001h (protected), 0000h (unprotected) secured silicon indicator bit (dq7, dq6) l l h ba x v id x x l x l l h h 00c4h (factory and customer locked), 0084h (factory locked), 0004h (not locked)
50 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information ta b l e 9 . pl127j boot sector/sector block addresses for protection/unprotection sector a22-a12 sector/ sector block size sector a22-a12 sector/ sector block size sa0 00000000000 4 kwords sa131-sa134 011111xxxxx 128 (4x32) kwords sa1 00000000001 4 kwords sa135-sa138 100000xxxxx 128 (4x32) kwords sa2 00000000010 4 kwords sa139-sa142 100001xxxxx 128 (4x32) kwords sa3 00000000011 4 kwords sa143-sa146 100010xxxxx 128 (4x32) kwords sa4 00000000100 4 kwords sa147-sa150 100011xxxxx 128 (4x32) kwords sa5 00000000101 4 kwords sa151-sa154 100100xxxxx 128 (4x32) kwords sa6 00000000110 4 kwords sa155-sa158 100101xxxxx 128 (4x32) kwords sa7 00000000111 4 kwords sa159-sa162 100110xxxxx 128 (4x32) kwords sa8 00000001xxx 32 kwords sa163-sa166 100111xxxxx 128 (4x32) kwords sa9 00000010xxx 32 kwords sa167-sa170 101000xxxxx 128 (4x32) kwords sa10 00000011xxx 32 kwords sa171-sa174 101001xxxxx 128 (4x32) kwords sa11-sa14 000001xxxxx 128 (4x32) kwords sa175-sa178 101010xxxxx 128 (4x32) kwords sa15-sa18 000010xxxxx 128 (4x32) kwords sa179-sa182 101011xxxxx 128 (4x32) kwords sa19-sa22 000011xxxxx 128 (4x32) kwords sa183-sa186 101100xxxxx 128 (4x32) kwords sa23-sa26 000100xxxxx 128 (4x32) kwords sa187-sa190 101101xxxxx 128 (4x32) kwords sa27-sa30 000101xxxxx 128 (4x32) kwords sa191-sa194 101110xxxxx 128 (4x32) kwords sa31-sa34 000110xxxxx 128 (4x32) kwords sa195-sa198 101111xxxxx 128 (4x32) kwords sa35-sa38 000111xxxxx 128 (4x32) kwords sa199-sa202 110000xxxxx 128 (4x32) kwords sa39-sa42 001000xxxxx 128 (4x32) kwords sa203-sa206 110001xxxxx 128 (4x32) kwords sa43-sa46 001001xxxxx 128 (4x32) kwords sa207-sa210 110010xxxxx 128 (4x32) kwords sa47-sa50 001010xxxxx 128 (4x32) kwords sa211-sa214 110011xxxxx 128 (4x32) kwords sa51-sa54 001011xxxxx 128 (4x32) kwords sa215-sa218 110100xxxxx 128 (4x32) kwords sa55-sa58 001100xxxxx 128 (4x32) kwords sa219-sa222 110101xxxxx 128 (4x32) kwords sa59-sa62 001101xxxxx 128 (4x32) kwords sa223-sa226 110110xxxxx 128 (4x32) kwords sa63-sa66 001110xxxxx 128 (4x32) kwords sa227-sa230 110111xxxxx 128 (4x32) kwords sa67-sa70 001111xxxxx 128 (4x32) kwords sa231-sa234 111000xxxxx 128 (4x32) kwords sa71-sa74 010000xxxxx 128 (4x32) kwords sa235-sa238 111001xxxxx 128 (4x32) kwords sa75-sa78 010001xxxxx 128 (4x32) kwords sa239-sa242 111010xxxxx 128 (4x32) kwords sa79-sa82 010010xxxxx 128 (4x32) kwords sa243-sa246 111011xxxxx 128 (4x32) kwords sa83-sa86 010011xxxxx 128 (4x32) kwords sa247-sa250 111100xxxxx 128 (4x32) kwords sa87-sa90 010100xxxxx 128 (4x32) kwords sa251-sa254 111101xxxxx 128 (4x32) kwords sa91-sa94 010101xxxxx 128 (4x32) kwords sa255-sa258 111110xxxxx 128 (4x32) kwords sa95-sa98 010110xxxxx 128 (4x32) kwords sa259 11111100xxx 32 kwords sa99-sa102 010111xxxxx 128 (4x32) kwords sa260 11111101xxx 32 kwords sa103-sa106 011000xxxxx 128 (4x32) kwords sa261 11111110xxx 32 kwords sa107-sa110 011001xxxxx 128 (4x32) kwords sa262 11111111000 4 kwords sa111-sa114 011010xxxxx 128 (4x32) kwords sa263 11111111001 4 kwords sa115-sa118 011011xxxxx 128 (4x32) kwords sa264 11111111010 4 kwords sa119-sa122 011100xxxxx 128 (4x32) kwords sa265 11111111011 4 kwords sa123-sa126 011101xxxxx 128 (4x32) kwords sa127-sa130 011110xxxxx 128 (4x32) kwords
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 51 advance information table 10. pl064j boot sector/sector block addresses for protection/unprotection sector a21-a12 sector/sector block size sa0 0000000000 4 kwords sa1 0000000001 4 kwords sa2 0000000010 4 kwords sa3 0000000011 4 kwords sa4 0000000100 4 kwords sa5 0000000101 4 kwords sa6 0000000110 4 kwords sa7 0000000111 4 kwords sa8 0000001xxx 32 kwords sa9 0000010xxx 32 kwords sa10 0000011xxx 32 kwords sa11-sa14 00001xxxxx 128 (4x32) kwords sa15-sa18 00010xxxxx 128 (4x32) kwords sa19-sa22 00011xxxxx 128 (4x32) kwords sa23-sa26 00100xxxxx 128 (4x32) kwords sa27-sa30 00101xxxxx 128 (4x32) kwords sa31-sa34 00110xxxxx 128 (4x32) kwords sa35-sa38 00111xxxxx 128 (4x32) kwords sa39-sa42 01000xxxxx 128 (4x32) kwords sa43-sa46 01001xxxxx 128 (4x32) kwords sa47-sa50 01010xxxxx 128 (4x32) kwords sa51-sa54 01011xxxxx 128 (4x32) kwords sa55-sa58 01100xxxxx 128 (4x32) kwords sa59-sa62 01101xxxxx 128 (4x32) kwords sa63-sa66 01110xxxxx 128 (4x32) kwords sa67-sa70 01111xxxxx 128 (4x32) kwords sa71-sa74 10000xxxxx 128 (4x32) kwords sa75-sa78 10001xxxxx 128 (4x32) kwords sa79-sa82 10010xxxxx 128 (4x32) kwords sa83-sa86 10011xxxxx 128 (4x32) kwords sa87-sa90 10100xxxxx 128 (4x32) kwords sa91-sa94 10101xxxxx 128 (4x32) kwords sa95-sa98 10110xxxxx 128 (4x32) kwords sa99-sa102 10111xxxxx 128 (4x32) kwords sa103-sa106 11000xxxxx 128 (4x32) kwords sa107-sa110 11001xxxxx 128 (4x32) kwords sa111-sa114 11010xxxxx 128 (4x32) kwords sa115-sa118 11011xxxxx 128 (4x32) kwords sa119-sa122 11100xxxxx 128 (4x32) kwords sa123-sa126 11101xxxxx 128 (4x32) kwords sa127-sa130 11110xxxxx 128 (4x32) kwords sa131 1111100xxx 32 kwords sa132 1111101xxx 32 kwords sa133 1111110xxx 32 kwords sa134 1111111000 4 kwords sa135 1111111001 4 kwords sa136 1111111010 4 kwords sa137 1111111011 4 kwords sa138 1111111100 4 kwords
52 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information selecting a sector protection mode the device is shipped with all sectors unprotected. optional spansion program - ming services enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a sector is protected or unprotected. see the secured silicon sector addresses for details. sa139 1111111101 4 kwords sa140 1111111110 4 kwords sa141 1111111111 4 kwords table 11. pl032j boot sector/sector block addresses for protection/unprotection sector a21-a12 sector/sector block size sa0 000000000 4 kwords sa1 000000001 4 kwords sa2 000000010 4 kwords sa3 000000011 4 kwords sa4 000000100 4 kwords sa5 000000101 4 kwords sa6 000000110 4 kwords sa7 000000111 4 kwords sa8 000001xxx 32 kwords sa9 000010xxx 32 kwords sa10 000011xxx 32 kwords sa11-sa14 0001xxxxx 128 (4x32) kwords sa15-sa18 0010xxxxx 128 (4x32) kwords sa19-sa22 0011xxxxx 128 (4x32) kwords sa23-sa26 0100xxxxx 128 (4x32) kwords sa27-sa30 0101xxxxx 128 (4x32) kwords sa31-sa34 0110xxxxx 128 (4x32) kwords sa35-sa38 0111xxxxx 128 (4x32) kwords sa39-sa42 1000xxxxx 128 (4x32) kwords sa43-sa46 1001xxxxx 128 (4x32) kwords sa47-sa50 1010xxxxx 128 (4x32) kwords sa51-sa54 1011xxxxx 128 (4x32) kwords sa55-sa58 1100xxxxx 128 (4x32) kwords sa59-sa62 1101xxxxx 128 (4x32) kwords sa63-sa66 1110xxxxx 128 (4x32) kwords sa67 111100xxx 32 kwords sa68 111101xxx 32 kwords sa69 111110xxx 32 kwords sa70 111111000 4 kwords sa71 111111001 4 kwords sa72 111111010 4 kwords sa73 111111011 4 kwords sa74 111111100 4 kwords sa75 111111101 4 kwords sa76 111111110 4 kwords sa77 111111111 4 kwords table 10. pl064j boot sector/sector block addresses for protection/unprotection sector a21-a12 sector/sector block size
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 53 advance information sector protection the pl127j, pl064j, and pl032j features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups. sector protection schemes password sector protection a highly sophisticated protection meth od that requires a password before changes to certain sectors or sector groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in sectors sa1- 133, sa1-134, sa2-0 and sa2-1. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. selecting a sector protection mode all parts default to operate in the pers istent sector protection mode. the cus - tomer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. if the persistent sector protection method is desired, programming the persistent sector protection mode locking bit permanently sets the device to the persistent sector protection mode. if the password sector protection method is desired, programming the password mode locking bit permanently sets the device to the password sector protection mode. it is not possible to switch between the two protection modes once a locking bit has been set. one of the two modes must be selected when the device is first programmed. this prevents a program or virus from later setting the password mode locking bit, which would cause an unexpected shift from the default per - sistent sector protection mode into the password protection mode. the device is shipped with all sectors unprotected. optional spansion program - ming services enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. ta b l e 1 2 . sector protection schemes dyb ppb ppb lock sector state 0 0 0 unprotected?ppb and dyb are changeable 0 0 1 unprotected?ppb not changeable, dyb is changeable 0 1 0 protected?ppb and dyb are changeable 1 0 0 1 1 0 0 1 1 protected?ppb not changeable, dyb is changeable 1 0 1 1 1 1
54 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information it is possible to determine whether a sector is protected or unprotected. see au - toselect mode for details. persistent sector protection the persistent sector protection method replaces the 12 v controlled protection method in previous flash devices. this new method provides three different sec - tor protection states: ? persistently locked?the sector is protected and cannot be changed. ? dynamically locked?the sector is protected and can be changed by a simple command. ? unlocked?the sector is unprotected and can be changed by a simple com - mand. to achieve these states, three types of ?bits? are used: ? persistent protection bit ? persistent protection bit lock ? persistent sector protection mode locking bit persistent protection bit (ppb) a single persistent (non-volatile) protecti on bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). all 4 kword boot-block sectors have individual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individually modifiable through the ppb write command. the device erases all ppbs in parallel. if any ppb requires erasure, the device must be instructed to preprogram all of the sector ppbs prior to ppb erasure. oth - erwise, a previously erased sector ppbs can potentially be over-erased. the flash device does not have a built-in means of preventing sector ppbs over-erasure. persistent protection bit lock (ppb lock) the persistent protection bit lock (ppb lock ) is a global volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cleared after power- up or hardware reset. there is no command sequence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modifiable through the dyb write command. when the parts are first shipped, the ppbs are cleared, the dybs are cleared, and ppb lock is defaulted to power up in the cleared state ? meaning the ppbs are changeable. when the device is first powered on the dybs power up cleared (sectors not pro - tected). the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write command sequences, the dybs will be set or cleared, thus placing each sector in the protected or unprotected state. these are the so- called dynamic locked or unlocked states. they are called dynamic states be - cause it is very easy to switch ba ck and forth betwee n the protected and unprotected conditions. this allows softwa re to easily protect sectors against in -
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 55 advance information advertent changes yet does not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and diffic ult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. indi - vidual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also lim - ited to 100 erase cycles. the ppb lock bit adds an additional level of protection. once all ppbs are pro - grammed to the desired settings, the ppb lock may be set to ?1?. setting the ppb lock disables all program and erase commands to the non-volatile ppbs. in ef - fect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed; for ex ample, to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system operation. the wp#/acc write protect pin adds a final level of hardware protection to sec - tors sa1-133, sa1-134, sa2-0 and sa2-1. when this pin is low it is not possible to change the contents of these sectors. these sectors generally hold system boot code. the wp#/acc pin can prevent an y changes to the boot code that could override the choices made while setting up sector protection during system initialization. for customers who are concerned about malicious viruses there is another level of security - the persistently locked state. to persistently protect a given sector or sector group, the ppbs associated with that sector need to be set to ?1?. once all ppbs are programmed to the desired settings, the ppb lock should be set to ?1?. setting the ppb lock automatically disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock ?freezes? the ppbs into their cur - rent state. the only way to clear the ppb lock is to go through a power cycle. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb write command se - quence is all that is necessary. the dyb write command for the dynamic sectors switch the dybs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to re - flect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. the best protection is achieved by executing the ppb lock bit set command early in the boot code, and protect the boot code by holding wp#/acc = vil. ta b l e 12 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or eras e a protected sector, the device ignores the command and returns to read mode. a program command to a protected sec - tor enables status polling for approximately 1 s before the device returns to read
56 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing a dyb/ppb/ppb lock verify co mmand to the device. there is an alter - native means of reading the protection st atus. take reset# to vil and hold we# at vih.(the high voltage a9 autoselect mode also works for reading the status of the ppbs). scanning the addresses (a18?a11 ) while (a6, a1, a0) = (0, 1, 0) will produce a logical ?1? code at device output dq0 for a protected sector or a ?0? for an unprotected sector. in this mode, the other addresses are don?t cares. address location with a1 = vil are reserved for autoselect manufacturer and device codes. persistent sector protec tion mode locking bit like the password mode locking bit, a pers istent sector protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode. password protection mode the password sector protection mode meth od allows an even higher level of se - curity than the persistent sector protection mode. there are two main differences between the persistent sector protection and the password sector protection mode: when the device is first powered on, or comes out of a reset cycle, the ppb lock bit set to the locked state, rather than cleared to the unlocked state. the only means to clear the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. once the password mode locking bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the password. the password may be correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password verify operations.
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 57 advance information once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. disables all further commands to the password region. all program, and read op - erations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the passwo rd is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after set - ting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persis - tent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands (see ?password verify command?). the password function work s in conjunction with the password mode locking bit, which when set, prevents the password verify command from reading the contents of the password on the pins of the device. write protect (wp#) the write protect feature provides a hardware method of protecting the upper two and lower two sectors without using v id . this function is provided by the wp# pin and overrides the previously discussed high voltage sector protection method. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two outermost 4 kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. if the system asserts v ih on the wp#/acc pin, the device reverts the upper two and lower two sectors to whether they were last set to be protected or unpro - tected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in the high voltage sector protection . note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode locking bit after power-up reset. if the password mode lock bit is also set after a hard ware reset (reset# asserted) or a power-up reset, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. assert - ing reset#, taking the device through a power-on reset, or issuing the ppb lock
58 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information bit set command sets the ppb lock bit to a ?1? when the password mode lock bit is not set. if the password mode locking bit is not se t, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set command. once set the only means for clear - ing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persistent protection mode. high voltage sector protection sector protection and unprotection may also be implemented using programming equipment. the procedure requires high voltage (v id ) to be placed on the re - set# pin. refer to figure 1 for details on this procedure. note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 59 advance information figure 1. in-system sector protection/sector unprotection algorithms sector protect: write 60h to sector address with a7-a0 = 00000010 set up sector address wait 100 s verify sector protect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7-a0 = 01000010 set up first sector address wait 1.2 ms verify sector unprotect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 remove v id from reset# write reset command sector protect complete remove v id from reset# write reset command sector unprotect complete
60 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information temporary sector unprotect this feature allows temporary unprotection of previously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be pro - grammed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. 2 shows the algorithm, and 21 shows the timing diagrams, for this feature. while ppb lock is set, the device cannot enter the temporary sector unprotection mode. secured silicon sector flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn) the 128-word secured silicon sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. the secured silicon sector is located at addresses 000000h-00007fh in both persistent protection mode and password protection mode. it uses indicator bits (dq6, dq7) to indicate the fac - tory-locked and customer-locked status of the part. the system accesses the secured silicon sector through a command sequence (see the enter secured silicon sector/exit secured silicon sector command se - quence ). after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses nor - mally occupied by the boot sectors. this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the de - vice reverts to sending commands to the normal address space. note that the acc function and unlock bypass modes are not available when the secured sili - con sector is enabled. notes: 1. all protected sectors unprotected (if wp#/acc = v il , upper two and lower two sectors will remain protected). 2. all previously protected sectors are protected once again figure 2. temporary sector unprotect operation start perform erase or program operations reset# = v ih te m p o ra r y s e c t o r unprotect completed (note 2) reset# = v id (note 1)
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 61 advance information factory-locked area (64 words) the factory-locked area of the secured silicon sector (000000h-00003fh) is locked when the part is shipped, whether or not the area was programmed at the factory. the secured silicon sector factory-locked indicator bit (dq7) is perma - nently set to a ?1?. optional spansion programming services can program the factory-locked area with a random esn, a customer-defined code, or any combi - nation of the two. because only spansion can program and protect the factory- locked area, this method ensures the security of the esn once the product is shipped to the field. contact your local sales office for details on using spansion?s programming services. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. customer-lockable area (64 words) the customer-lockable area of the secured silicon sector (000040h-00007fh) is shipped unprotected, which allows the cust omer to program and optionally lock the area as appropriate for the application. the secured silicon sector customer- locked indicator bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secured silicon protection bit program command. the secured sil - icon sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass func - tions are not available when programming the secured silicon sector. the customer-lockable secured silicon sector area can be protected using one of the following procedures: ? write the three-cycle enter secured silicon sector region command se - quence, and then follow the in-system sector protect algorithm as shown in figure 1 , except that reset# may be at either v ih or v id . this allows in-sys - tem protection of the secured silicon sector region without raising any de - vice pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure 3 . once the secured silicon sector is locked and verified, the system must write the exit secured silicon sector region comm and sequence to return to reading and writing the remainder of the array. the secured silicon sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. secured silicon sector protection bits the secured silicon sector protection bits prevent programming of the secured silicon sector memory area. once set, the secured silicon sector memory area contents are non-modifiable.
62 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. in addition, the following hardware data protection measures prev ent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro - tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, ce#, or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. figure 3. secured silicon sector protect verify write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 63 advance information common flash memory interface (cfi) the common flash interface (cfi) specificati on outlines device and host system software interrogation handshake, which allows specific vendor-specified soft - ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back - ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 13 ? 16 . to terminate reading cfi data, the system must write the reset command. the cfi query mode is not accessible when the device is executing an embedded program or embedded erase algorithm. the system can also write the cfi query command when the device is in the au - toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 13 ? 16 . the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100. contact your local sales office for copies of these documents. ta b l e 1 3 . cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
64 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information ta b l e 1 4 . system interface string addresses data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0003h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) ta b l e 1 5 . device geometry definition addresses data description 27h 0018h (pl127j) 0017h (pl064j) 0016h (pl032j) device size = 2 n byte 28h 29h 0001h 0000h flash device interface descriptio n (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 00fdh (pl127j) 007dh (pl064j) 003dh (pl032j) erase block region 2 information (refer to the cfi specification or cfi publication 100) 32h 33h 34h 0000h 0000h 0001h 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 65 advance information ta b l e 1 6 . primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii (reflects modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h tbd address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h (plxxxj) sector protect/unprotect scheme 07 = advanced sector protection 4ah 00e7h (pl127j) 0077h (pl064j) 003fh (pl032j) simultaneous operation 00 = not supported, x = number of sectors excluding bank 1 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h (plxxxj) page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = uniform device, 01h = both top and bottom boot with write protect, 02h = bottom boot device, 03h = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0027h (pl127j) 0017h (pl064j) 000fh (pl032j) bank 1 region information x = number of sectors in bank 1 59h 0060h (pl127j) 0030h (pl064j) 0018h (pl032j) bank 2 region information x = number of sectors in bank 2 5ah 0060h (pl127j) 0030h (pl064j) 0018h (pl032j) bank 3 region information x = number of sectors in bank 3
66 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information command definitions writing specific address and data commands or sequences into the command register initiates device operations. ta b l e 17 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset com - mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristic section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded prog ram or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. the system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase re - sume commands section for more information. the system must issue the reset command to return a bank to the read (or erase- suspend-read) mode if dq5 goes high during an active program or erase opera - tion, or if the bank is in the autoselect mode. see the next section, reset command , for more information. see also requirements for reading array data in the device bus operations sec - tion for more information. the ac characteristic table provides the read parameters, and figure 12 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys - tem was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. 5bh 0027h (pl127j) 0017h (pl064j) 000fh (pl032j) bank 4 region information x = number of sectors in bank 4 table 16. primary vendor-specific extended query (continued) addresses data description
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 67 advance information the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autosele ct mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manu - facturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle th at contains the bank address and the au - toselect command. the bank then enters the autoselect mode. the system may read any number of autoselect codes without reinitiating the command sequence. ta b l e 17 shows the address and data requirements. to determine sector protec - tion information, the system must write to the appropriate bank address (ba) and sector address (sa). tab l e 3 shows the address range and bank number associ - ated with each sector. the system must write the reset command to return to the read mode (or erase- suspend-read mode if the bank wa s previously in erase suspend). enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing a ran - dom, eight word electronic serial number (esn). the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues th e four-cycle exit secured silicon sector command sequence. the exit secured silicon sector command sequence returns the device to normal operation. the secured silicon sector is not accessible when the device is executing an embedded program or embedded erase algorithm. ta b l e 17 shows the address and data requirem ents for both command sequences. see also ?secured silicon sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. word program command sequence programming is a four-bus-cycle operat ion. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com - mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con - trols or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. ta b l e 17 shows the address and data requirements for the program command sequence. note that the secured
68 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information silicon sector, autoselect, and cfi functi ons are unavailable when a [program/ erase] operation is in progress. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write operation status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. note that the secured silicon sector, autoselect and cfi functions are unavailable when the secured sil - icon sector is enabled. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. the unlock bypass com - mand sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this se - quence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. tab l e 17 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by - pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (see table 18 ) the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en - ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device damage may result. in addition, the wp#/acc pin must not be left floating or uncon - nected; inconsistent behavior of the device may result. 4 illustrates the algorithm for the program operation. refer to the erase/program operations table in the ac characteristics section for parameters, and figure 14 for timing diagrams.
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 69 advance information chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini - tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto - matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is no t required to provide any controls or tim - ings during these operations. ta b l e 17 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latche d. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. note that se - cured silicon sector, autoselect, and cfi functions are unavailable when a [program/erase] operation is in progress. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase com - mand sequence should be reinitiated on ce that bank has returned to reading array data, to ensure data integrity. note: see table 17 for program command sequence. figure 4. program operation start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
70 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information 5 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ac characteristics section for parameters, and figure 16 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi - tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. ta b l e 17 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em - bedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electr ical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com - mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any com - mand other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system must rewrite the com - mand sequence and any additional addresses and commands. note that secured silicon sector, autoselect, and cfi functi ons are unavailable when a [program/ erase] operation is in progress. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer). the time-out begins from the ris - ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to the write operation sta - tus section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im - mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. 5 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ac characteristics section for parameters, and figure 16 section for timing diagrams.
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 71 advance information erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this com - mand is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. how - ever, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. after the erase operation has been suspended, the bank enters the erase-sus - pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta - tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program notes: 1. see table 17 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. figure 5. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
72 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the syst em can also issue the autoselect com - mand sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes ar e not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. refer to the secured silicon sec - tor addresses and the autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command (address bits are don?t care). the bank address of the erase-sus - pended bank is required when writin g this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. if the persistent sector protection mode locking bit is verified as programmed without margin, the persistent sector protection mode locking bit program com - mand should be reissued to improve program margin. if the secured silicon sector protection bit is verified as programmed without margin, the secured sil - icon sector protection bit program command should be reissued to improve program margin. ? after programming a ppb, two additional cycles are needed to determine whether the ppb has been programmed with margin. if the ppb has been programmed without margin, the program command should be reissued to improve the program margin. also note that the total number of ppb program/ erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. if the ppbs has been erased without mar - gin, the erase command should be reissued to improve the program margin. the programming of either the ppb or dyb for a given sector or sector group can be verified by writing a sector protection status command to the device. note that there is no single command to independently verify the programming of a dyb for a given sector group. command definitions tables ta b l e 1 7 . memory array command definitions command (notes) cycles bus cycles (notes 1 ? 4 ) addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 01 device id (note 10) 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 227e (ba) x0e (note 10) (ba) x0f (note 10) secured silicon sector factory protect (note 8) 4 555 aa 2aa 55 (ba) 555 90 x03 (note 8) sector group protect verify (note 9) 4 555 aaa 2aa 55 (ba) 555 90 (sa) x02 xx00/ xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 11) 1 ba b0
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 73 advance information program/erase resume (note 12) 1 ba 30 cfi query (note 13) 1 55 98 accelerated program (note 15) 2 xx a0 pa pd unlock bypass entry (note 15) 3 555 aa 2aa 55 555 20 unlock bypass program (note 15) 2 xx a0 pa pd unlock bypass erase (note 15) 2 xx 80 xx 10 unlock bypass cfi (notes 13 , 15 ) 1 xx 98 unlock bypass reset (note 15) 2 xxx 90 xxx 00 ta b l e 1 8 . sector protection command definitions command (notes) cycles bus cycles (notes 1 - 4 ) addr data addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secured silicon sector entry 3 555 aa 2aa 55 555 88 secured silicon sector exit 4 555 aa 2aa 55 555 90 xx 00 secured silicon protection bit program (notes 5 , 6 ) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd(0) secured silicon protection bit status 5 555 aa 2aa 55 555 60 ow 48 ow rd(0) password program (notes 5 , 7 , 8 ) 4 555 aa 2aa 55 555 38 xx[0-3] pd[0-3] table 17. memory array command definitions command (notes) cycles bus cycles (notes 1 ? 4 ) addr data addr data addr data addr data addr data addr data legend: ba = address of bank switching to autoselect mode, bypass mode, or erase operation. determined by pl127j: amax:a20, pl064j: amax:a19, pl032j: amax:a18. pa = program address (amax:a0). addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data (dq15:dq0) written to location pa. data latches on rising edge of we# or ce# pulse, whichever happens first. ra = read address (amax:a0). rd = read data (dq15:dq0) from location ra. sa = sector address (amax:a12) for verifying (in autoselect mode) or erasing. wd = write data. see ?configuration register? definition for specific write data. data latched on rising edge of we#. x = don?t care notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to reading array (or to erase-suspend-read mode if previously in erase suspend) when bank is in autoselect mode, or if dq5 goes high (while bank is prov iding status information). 7. fourth cycle of autoselect command sequence is a read cycle. system must provid e bank address to obtain manufacturer id or device id information. see autoselect command sequence section for more information. 8. the data is c4h for factory and customer locked, 84h for factory locked and 04h for not locked. 9. the data is 00h for an unprotected sector group and 01h fo r a protected sector group. 10. device id must be read across cycles 4, 5, and 6. pl127j (x0eh = 2220h, x0fh = 2200h),pl064j (x0eh = 2202h, x0fh = 2201h), pl032j (x0eh = 220ah, x0fh = 2201h). 11. system may read and program in non-erasing sectors, or enter autoselect mode, when in program/erase suspend mode. program/erase suspend command is valid only during a sector erase operation, and requires bank address. 12. program/erase resume command is valid only during erase suspend mode, and requires bank address. 13. command is valid when device is ready to read array data o r when device is in autoselect mode. 14. wp#/acc must be at v id during the entire operation of command. 15. unlock bypass entry command is required prior to any unlock bypass operation. unlock bypass reset command is required to return to the reading array.
74 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information write operation status the device provides several bits to determine the status of a program or erase opera - tion: dq2, dq3, dq5, dq6, and dq7. ta b l e 19 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a password verify (notes 6 , 8 , 9 ) 4 555 aa 2aa 55 555 c8 pwa[0-3] pwd[0-3] password unlock (notes 7 , 10 , 11 ) 7 555 aa 2aa 55 555 28 pwa[0] pwd[0] pwa[1] pwd[1] pwa[2] pwd[2] pwa[3] pwd[3] ppb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 (sa)wp 68 (sa)wp 48 (sa)wp rd(0) ppb status 4 555 aa 2aa 55 555 90 (sa)wp rd(0) all ppb erase (notes 5 , 6 , 13 , 14 ) 6 555 aa 2aa 55 555 60 wp 60 (sa) 40 (sa)wp rd(0) ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status (note 15) 4 555 aa 2aa 55 555 58 sa rd(1) dyb write (note 7) 4 555 aa 2aa 55 555 48 sa x1 dyb erase (note 7) 4 555 aa 2aa 55 555 48 sa x0 dyb status (note 6) 4 555 aa 2aa 55 555 58 sa rd(0) ppmlb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status (note 5) 5 555 aa 2aa 55 555 60 pl 48 pl rd(0) spmlb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status (note 5) 5 555 aa 2aa 55 555 60 sl 48 sl rd(0) table 18. sector protection command definitions legend: d yb = dynamic protection bit o w = address (a7:a0) is (00011010) p d[3:0] = password data (1 of 4 portions) p pb = persistent protection bit p wa = password address. a1:a0 selects portion of password. p wd = password data being verified. p l = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. sa = sector address where security command applies. address bits amax:a12 uniquely select any sector. sl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit n otes: 1. see table 1 for description of bus operations. 2 . all values are in hexadecimal. 3 . shaded cells in table denote read cycles. all other cycles are write operations. 4 . during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5 . the reset command returns device to reading array. 6 . cycle 4 programs the addressed locking bit. cycles 5 and 6 validate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8 . entire command sequence must be entered for each portion of password. 9. command sequence returns ffh if ppmlb is set. 10. the password is written over four consecutive cycles, at addresses 0-3. 11. a 2 s timeout is required between any two portions of password. 12. a 100 s timeout is required between cycles 4 and 5. 13. a 1.2 ms timeout is required between cycles 4 and 5. 14. cycle 4 erases all ppbs. cycles 5 and 6 validate bits have been fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase command must be issued and verified again. before issuing erase command, all ppbs should be programmed to prevent ppb overerasure. 15. dq1 = 1 if ppb locked, 0 if unlocked.
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 75 advance information hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded pro - gram or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the com - mand sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device out - puts the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1 ? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status in - formation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 400 s, then the bank returns to the read mode. if not al l selected sectors are protected, the em - bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq15?dq0 on the following read cycles. just prior to the completion of an embedded program or erase operation, dq7 may change asyn - chronously with dq15?dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 will appear on successive read cycles. ta b l e 19 shows the outputs for data# polling on dq7. 6 shows the data# polling algorithm. 18 in the ac characteristic section shows the data# polling timing diagram.
76 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information ry / b y # : r e a d y / b u s y # the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. ta b l e 19 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 6. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 77 advance information of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy - cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the op eration is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 400 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo - rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac - tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en - ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter - natively, the system can use dq7 (see the dq7: data# polling ). if a program address falls within a pr otected sector, dq6 toggles for approxi - mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e 19 shows the outputs for toggle bit i on dq6. figure 7 shows the toggle bit algorithm. figure 19 in ?read operation timings? shows the toggle bit timing di - agrams. figure 20 shows the differences between dq2 and dq6 in graphical form. see also the dq2: toggle bit ii .
78 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are re quired for sector and mode information. refer to ta b l e 19 to compare outputs for dq2 and dq6. figure 7 shows the toggle bit algorithm in flowchart form, and the dq2: toggle bit ii explains the algorithm. see also the dq6: toggle bit i . figure 19 shows the toggle bit timing diagram. figure 20 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 7 for the following discussion. whenever the system initially be - gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the dq6: toggle bit i and dq2: toggle bit ii for more information. figure 7. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 79 advance information store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has comple ted the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc - cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system in itially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de - scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo - rithm when it returns to determine the status of the operation (top of figure 7 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified inter - nal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the opera - tion, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspen d-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de - termine whether or not erasure has beg un. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? see also the sector erase command sequence . after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further comman ds (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi - tional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each sub - sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 19 shows the status of dq3 relative to the other status bits.
80 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs arra y data if the system addresses a non-busy bank. ta b l e 1 9 . write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# to g g l e 0 n/a no toggle 0 embedded erase algorithm 0 to g g l e 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# to g g l e 0 n/a n/a 0
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 81 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v reset# (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +13.0 v wp#/acc (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8 . maximum dc input voltage on pin a9, oe#, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute max- imum rating conditions for extended periods may affect device reliability. figure 8. maximum overshoot waveforms 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v maximum negative overshoot waveform maximum positive overshoot waveform
82 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information operating ranges operating ranges define those limits between which the functionality of the de - vice is guaranteed. industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c wireless devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7?3.1 v v io (see note) . . 1.65?1.95 v (for pl127j) or 2.7?3.1 v (for all plxxxj devices) notes: for all ac and dc specifications, v io = v cc ; contact your local sales office for other v io options.
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 83 advance information dc characteristics notes: 1. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v ccmax . 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 1 m a. 5. not 100% tested. 6. valid ce1#/ce2# conditions: (ce1# = v il, ce2# = v ih, ) or (ce1# = v ih, ce2# = v il ) or (ce1# = v ih, ce2# = v ih ) ta b l e 2 0 . cmos compatible parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, reset# input load current v cc = v cc max ; v id = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; v id = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1 , 2 ) oe# = v ih , v cc = v cc max (note 1) 5 mhz 15 25 ma 10 mhz 45 55 i cc2 v cc active write current (notes 2 , 3 ) oe# = v ih , we# = v il 15 25 ma i cc3 v cc standby current (note 2) ce#, reset#, wp#/acc = v io 0.3 v 0.2 5 a i cc4 v cc reset current (note 2) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 ) v ih = v io 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 v cc active read-while-program current (notes 1 , 2 ) oe# = v ih , 5 mhz 21 45 ma 10 mhz 46 70 i cc7 v cc active read-while-erase current (notes 1 , 2 ) oe# = v ih , 5 mhz 21 45 ma 10 mhz 46 70 i cc8 v cc active program-while-erase- suspended current (notes 2 , 5 ) oe# = v ih 17 25 ma i cc9 v cc active page read current (note 2) oe# = v ih , 8 word page read 10 15 ma v il input low voltage v io = 1.65?1.95 v (pl127j) ?0.4 0.4 v v io = 2.7?3.6 v ?0.5 0.8 v v ih input high voltage v io = 1.65?1.95 v (pl127j) v io ?0.4 v io +0.4 v v io = 2.7?3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 100 a, v cc = v cc min , v io = 1.65? 1.95 v (pl127j) 0.1 v i ol = 2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 0.4 v v oh output high voltage i oh = ?100 a, v cc = v cc min , v io = 1.65? 1.95 v (pl127j) v io ?0.1 v i oh = ?2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 2.4 v v lko low v cc lock-out voltage (note 5) 2.3 2.5 v
84 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information ac characteristic test conditions note: diodes are in3064 or equivalent figure 9. te s t s e t u p s ta b l e 2 1 . test specifications test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times v io = 1.8 v (pl127j) 5 ns v io = 3.0 v input pulse levels v io = 1.8 v (pl127j) 0.0 - 1.8 v v io = 3.0 v 0.0?3.0 input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v 2.7 k ? c l 6.2 k ? 3 . 6 v device under te s t c l device under tes t v io = 3.0 v v io = 1.8 v (pl127j)
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 85 advance information switching waveforms vcc ramprate all dc characteristics are specified for a v cc ramp rate > 1v/100 s and v cc >=v ccq - 100 mv. if the v cc ramp rate is < 1v/100 s, a hardware reset required. table 22. key to switching waveforms waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) figure 10. input waveforms and measurement levels vio 0.0 v vio/2 vio/2 output measurement level in
86 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information read operations notes: 1. not 100% tested. 2. see figure 9 and table 21 for test specifications. 3. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . 4. for 70pf output load capacitance, 2 ns will be added to the above t acc ,t ce ,t pacc ,t oe values for all speed grades. ta b l e 2 3 . read-only operations parameter description te s t s e t u p speed options jedec std. 55 60 65 70 unit t avav t rc read cycle time (note 1) min 55 60 65 70 ns t avqv t acc address to output delay ce#, oe# = v il max 55 60 65 70 ns t elqv t ce chip enable to output delay oe# = v il max 55 60 65 70 ns t pacc page access time max 20 25 30 ns t glqv t oe output enable to output delay max 20 25 30 ns t ehqz t df chip enable to output high z (note 3) max 16 ns t ghqz t df output enable to output high z (notes 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 3) min 5 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns figure 11. read operation timings t oh t ce data we# addresses ce# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 87 advance information reset note: not 100% tested. figure 12. page read operation timings ta b l e 2 4 . hardware reset (reset#) parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 35 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns amax - a3 ce# oe# a2 - a0 data same page aa ab ac ad qa qb qc qd t acc t pacc t pacc t pacc
88 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information figure 13. reset timings reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 89 advance information erase/program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. ta b l e 2 5 . erase and program operations parameter speed options jedec std description 55 60 65 70 unit t avav t wc write cycle time (note 1) min 55 60 65 70 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 30 35 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 25 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 40 ns t whdl t wph write pulse width high min 20 25 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) typ 6 s t whwh1 t whwh1 accelerated programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
90 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information timing diagrams notes: 1. pa = program address, pd = program data, d out is the true data at the program address figure 14. program operation timings figure 15. accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 91 advance information notes: 1. sa = sector address (for sector erase), va = valid address for reading status data ( see ?write operation status? figure 16. chip/sector erase operation timings figure 17. back-to-back read/write cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t ce t ah valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as
92 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle figure 18. data# polling timings (during embedded algorithms) notes: 1. va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 19. toggle bit timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by#
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 93 advance information protect/unprotect note: not 100% tested. note: note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 20. dq2 vs. dq6 ta b l e 2 6 . temporary sector unprotect parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s figure 21. temporary sector unprotect timing diagram enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr v id v il or v ih v id v il or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
94 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information notes: 1. for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 22. sector/sector block protect and unprotect timing diagram sector group protect: 150 s sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 95 advance information controlled erase operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. ta b l e 2 7 . alternate ce# controlled erase and program operations parameter speed options jedec std description 55 60 65 70 unit t avav t wc write cycle time (note 1) min 55 60 65 70 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 30 35 ns t dveh t ds data setup time min 25 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 40 ns t ehel t cph ce# pulse width high min 20 25 ns t whwh1 t whwh1 programming operation (note 2) typ 6 s t whwh1 t whwh1 accelerated programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec
96 s29pl127j/s29pl064j/s29pl032j for mcp s29pl127j_064j_032j_mcp_00_a3 august 12, 2004 advance information notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device ta b l e 2 8 . alternate ce# controlled write (erase/program) operation timings t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
august 12, 2004 s29pl127j_064j_032j_mcp_00_a3 s29pl127j/s29pl064j/s29pl032j for mcp 97 advance information notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pa ttern. all values are subject to change. 2. under worst case conditions of 90 c, v cc = 2.7 v, 100,000 cycles. all values are subject to change. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 17 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 100,000 cycles. bga pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. ta b l e 2 9 . erase and programming performance parameter ty p (note 1) max (note 2) unit comments sector erase time 0.5 2 sec excludes 00h programming prior to erasure (note 4) chip erase time pl127j 135 216 sec pl064j 71 113.6 sec pl032j 39 62.4 sec word program time 6 100 s excludes system level overhead (note 5) accelerated word program time 4 60 s chip program time (note 3) pl127j 50.4 200 sec pl064j 25.2 50.4 sec pl032j 12.6 25.2 sec parameter symbol parameter description te s t s e t u p ty p max unit c in input capacitance v in = 0 6.3 7 pf c out output capacitance v out = 0 7.0 8 pf c in2 control pin capacitance v in = 0 5.5 8 pf c in3 wp#/acc pin capacitance v in = 0 11 12 pf
98 type 2 psram psram_type02_15a0 may 3, 2004 advance information type 2 psram 16mb (1mb word x 16-bit) 32mb (2mb word x 16-bit) 64mb (4mb word x 16-bit) features ? process technology: cmos ? organization: x16 bit ? power supply voltage: 2.7~3.1v ? three state outputs ? compatible with low power sram product information pin description density v cc range standby (isb1, max.) operating (icc2, max.) mode 16mb 2.7-3.1v 80 a 30 ma dual cs 16mb 2.7-3.1v 80 a 35 ma dual cs and page mode 32mb 2.7-3.1v 100 a 35 ma dual cs 32mb 2.7-3.1v 100 a 40 ma dual cs and page mode 64mb 2.7-3.1v tbd tbd dual cs 64mb 2.7-3.1v tbd tbd dual cs and page mode pin name description i/o cs1#, cs2 chip select i oe# output enable i we# write enable i lb#, ub# lower/upper byte enable i a0-a19 (16m) a0-a20 (32m) a0-a21 (64m) address inputs i i/o0-i/o15 data inputs/outputs i/o v cc /v ccq power supply ? v ss /v ssq ground ? nc not connection ? dnu do not use ?
may 3, 2004 psram_type02_15a0 type 2 psram 99 advance information power up sequence 1. apply power. 2. maintain stable power (v cc min.=2.7v) for a minimum 200 s with cs1#=high or cs2=low. timing diagrams power up notes: 1. after v cc reaches v cc (min.), wait 200 s with cs1# high. then the device gets into the normal operation. notes: 1. after v cc reaches v cc (min.), wait 200 s with cs2 low. then the device gets into the normal operation. figure 23. power up 1 (cs1# controlled) figure 24. power up 2 (cs2 controlled) min. 200 s v cc cs 1# cs2 v cc(min) normal operation power up mode min. 200 s v cc cs1# cs2 v cc(min) normal operation power up mode
100 type 2 psram psram_type02_15a0 may 3, 2004 advance information functional description legend: x = don?t care (must be low or high state). absolute maximum ratings notes: 1. stresses greater than those listed under " absolute maximum ratings " section may cause permanent damage to the device. functional operation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reliability. dc recommended operating conditions notes: 1. ta=-40 to 85c, otherwise specified. 2. overshoot: v cc +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. mode cs1# cs2 oe# we# lb# ub# i/o 1-8 i/o 9-16 power deselected h x x x x x high-z high-z standby deselected x l x x x x high-z high-z standby deselected x x x x h h high-z high-z standby output disabled l h h h l x high-z high-z active outputs disabled l h h h x l high-z high-z active lower byte read l h l h l h d out high-z active upper byte read l h l h h l high-z d out active word read l h l h l l d out d out active lower byte write l h x l l h d in high-z active upper byte write l h x l h l high-z d in active word write l hxlll d in d in active item symbol ratings unit voltage on any pin relative to v ss v in , v out -0.2 to v cc +0.3v v voltage on v cc supply relative to v ss v cc -0.2 to 3.6v v power dissipation p d 1.0 w operating temperature t a -40 to 85 c symbol parameter min ty p max unit v cc power supply voltage 2.7 2.9 3.1 v v ss ground 0 0 0 v ih input high voltage 2.2 ? v cc + 0.3 (note 2) v il input low voltage -0.2 (note 3) ? 0.6
may 3, 2004 psram_type02_15a0 type 2 psram 101 advance information capacitance (ta = 25c, f = 1 mhz) note: this parameter is sampled periodically and is not 100% tested. dc and operating characteristics common symbol parameter test condition min max unit c in input capacitance v in = 0v ? 8 pf c oio input/output capacitance v out = 0v ? 10 pf item symbol test conditions min ty p max unit input leakage current i li v in =v ss to v cc -1 ? 1 a output leakage current i lo cs1#=v ih or cs2=v il or oe#=v ih or we#=v il or lb#=ub#=v ih , v io =v ss to v cc -1 ? 1 a output low voltage v ol i ol =2.1ma ? ? 0.4 v output high voltage v oh i oh =-1.0ma 2.4 ? ? v
102 type 2 psram psram_type02_15a0 may 3, 2004 advance information 16m psram notes: 1. standby mode is supposed to be set up after at least one active operation after power up. isb1 is measure after 60ms from the time when standby mode is set up. 32m psram notes: 1. standby mode is supposed to be set up after at least one active operation after power up. isb1 is measure after 60ms from the time when standby mode is set up. item symbol test conditions min ty p max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, lb# 0.2v and/or ub# 0.2v, cs2 v cc -0.2v, v in 0.2v or v in vcc-0.2v ? ? 7 ma i cc2 async cycle time=min, i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in =v ih or v il ? ? 30 ma page cycle time=t rc +3t pc , i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in -v ih or v il 35 ma standby current (cmos) i sb1 (note 1) other inputs=0-vcc 1. cs1# v cc - 0.2, cs2 v cc - 0.2v (cs1# controlled) or 2. 0v cs2 0.2v (cs2 controlled) ? ? 80 ma item symbol test conditions min ty p max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, lb# 0.2v and/or ub# 0.2v, cs2 v cc -0.2v, v in 0.2v or v in vcc-0.2v ? ? 7 ma i cc2 async cycle time=min, i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in =v ih or v il ? ? 35 ma page cycle time=t rc +3t pc , i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in -v ih or v il 40 ma standby current (cmos) i sb1 (note 1) other inputs=0-vcc 1. cs1# v cc - 0.2, cs2 v cc - 0.2v (cs1# controlled) or 2. 0v cs2 0.2v (cs2 controlled) ? ? 100 ma
may 3, 2004 psram_type02_15a0 type 2 psram 103 advance information 64m psram notes: 1. standby mode is supposed to be set up after at least one active operation after power up. isb1 is measure after 60ms from the time when standby mode is set up. ac operating conditions test conditions (test load and test input/output reference) ? input pulse level: 0.4 to 2.2v ? input rising and falling time: 5ns ? input and output reference voltage: 1.5v ? output load (see figure 25 ): cl=50pf note: including scope and jig capacitance. item symbol test conditions min ty p max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, lb# 0.2v and/or ub# 0.2v, cs2 v cc -0.2v, v in 0.2v or v in vcc-0.2v ? ? tbd ma i cc2 async cycle time=min, i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in =v ih or v il ? ? tbd ma page cycle time=t rc +3t pc , i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in -v ih or v il tbd ma standby current (cmos) i sb1 (note 1) other inputs=0-vcc 1. cs1# v cc - 0.2, cs2 v cc - 0.2v (cs1# controlled) or 2. 0v cs2 0.2v (cs2 controlled) ? ? tbd ma figure 25. output load c l dout
104 type 2 psram psram_type02_15a0 may 3, 2004 advance information acc characteristics (ta = -40c to 85c, v cc = 2.7 to 3.1 v) notes: 1. t wp (min)=70ns for continuous write operation over 50 times. symbol parameter speed bins unit 70ns min max read t rc read cycle time 70 ? ns t aa address access time ? 70 ns t co chip select to output ? 70 ns t oe output enable to valid output ? 35 ns t ba ub#, lb# access time ? 70 ns t lz chip select to low-z output 10 ? ns t blz ub#, lb# enable to low-z output 10 ? ns t olz output enable to low-z output 5 ? ns t hz chip disable to high-z output 0 25 ns t bhz ub#, lb# disable to high-z output 0 25 ns t ohz output disable to high-z output 0 25 ns t oh output hold from address change 5 ? ns t pc page cycle time 25 ? ns t pa page access time ? 20 ns write t wc write cycle time 70 ? ns t cw chip select to end of write 60 ? ns t as address set-up time 0 ? ns t aw address valid to end of write 60 ? ns t bw ub#, lb# valid to end of write 60 ? ns t wp write pulse width 55 (note 1) ? ns t wr write recovery time 0 ? ns t whz write to output high-z 0 25 ns t dw data to write time overlap 30 ? ns t dh data hold from write time 0 ? ns t ow end write to output low-z 5 ? ns
may 3, 2004 psram_type02_15a0 type 2 psram 105 advance information timing diagrams read timings notes: 1. address controlled, cs1#=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il . notes: 1. we#=v ih . notes: figure 26. timing waveform of read cycle(1) figure 27. timing waveform of read cycle(2) figure 28. timing waveform of read cycle(2) address data out previous data valid data valid t aa t rc t oh data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t co address ub#, lb# oe# data out cs1# cs2 data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa high z a1~a0 dq15~dq0 oe# t ohz t oe t co t aa cs1# cs2 address 1)
106 type 2 psram psram_type02_15a0 may 3, 2004 advance information 1. 16mb: a2 ~ a19, 32mb: a2 ~ a20, 64mb: a2 ~ a21. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. t oe (max) is met only when oe# becomes enabled after t aa (max). if invalid address signals shorter than min. t rc are continuously repeated for over 4s, the device needs a normal read timing (t rc ) or needs to sustain standby state for min. t rc at least once in every 4s. write timings figure 29. write cycle #1 (we# controlled) figure 30. write cycle #2 (cs1# controlled) address cs1# data undefined ub#, lb# we# data in data out t wc t cw t wr t aw t bw t wp t as t dh t dw t whz t ow high-z high-z data valid cs2 address data valid ub#, lb# we# data in data out high-z t wc t cw t aw t bw t wp t dh t dw t wr t as cs1# cs2
may 3, 2004 psram_type02_15a0 type 2 psram 107 advance information notes: 1. a write occurs during the overlap(t wp ) of low cs1# and low we#. a write begins when cs1# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs1# goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs1# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs1# or we# going high. figure 31. timing waveform of write cycle(3) (cs2 controlled) figure 32. timing waveform of write cycle(4) (ub#, lb# controlled) address data valid ub#, lb# we# data in data out high-z t wc t cw t aw t bw t wp(1) t dh t dw t wr t as cs1# cs2 address data valid ub #, lb# we# data in data out high-z t wc t cw t bw t wp t dh t dw t wr t aw t as cs1# cs2
108 psram type 3 psram_type03_06a0 february 25, 2004 advance information psram type 3 16 megabit (1m x 16) cmos pseudo sram features ? organized as 1m words by 16 bits ? fast cycle time: 70 ns ? standby current: 100 a ? deep power-down current: 10 a (memory cell data invalid) ? byte data control: lb# (dq0 - 7), ub# (dq8 - 15) ? compatible with low-power sram ? single power supply voltage: 3.0v0.3v description psram type 3 currently includes only a 16m bit device, organized as 1m words by 16 bits. it is designed with advanced cmos technology specified ram featur - ing low-power static ram-compatible functi on and pin configuration. this device operates from a single power supply. adva nced circuit technology provides both high speed and low power. it is automati cally placed in low-power mode when cs1# or both ub# and lb# are asserted hi gh or cs2 is asserted low. there are three control inputs. cs1# and cs2 are us ed to select the device, and output en - able (oe#) provides fast memory acce ss. data byte control pins (lb#,ub#) provide lower and upper byte access. this device is well suited to various micro - processor system applications where high speed, low power and battery backup are required. pin description a0 ? a19 = address inputs dq0 ? dq15 = data inputs/outputs ce1# = chip enable ce2 = deep power down oe# = output enable we# = write control lb# = lower byte control ub# = upper byte control vcc = power supply vss = ground
february 25, 2004 psram_type03_06a0 psram type 3 109 advance information operation mode note: x = don?t care. h = logic high. l = logic low. absolute maximum ratings (see note) note: absolute maximum dc requirements contains stress rating s only. functional operation at the absolute maximum limits is not implied or guaranteed. extended exposu re to maximum ratings may affect device reliability. dc characteristics notes: 1. overshoot: v cc + 2.0v in case of pulse width 20ns 2. undershoot: -2.0v in case of pulse width 20ns 3. overshoot and undershoot are sampled, not 100% tested. mode ce1# ce2 oe# we# lb# ub# dq0 to dq7 dq8 to dq15 power deselect h h x x x x high-z high-z standby deselect x l x x x x high-z high-z deep power down deselect l h x x h h high-z high-z standby output disabled l h h h l x high-z high-z active output disabled l h h h x l high-z high-z active lower byte read l h l h l h d-out high-z active upper byte read l h l h h l high-z d-out active word read l h l h l l d-out d-out active lower byte write l h x l l h d-in high-z active upper byte write l h x l h l high-z d-in active word write l h x l l l d-in d-in active symbol rating value unit v cc supply voltage -0.2 to +3.6 v v in input voltages -0.2 to v cc + 0.3 v v in , v out output and output voltages -2.0 to +3.6 v i sh output short circuit current 100 ma p d power dissipation 1 w ta b l e 3 0 . dc recommended operating conditions symbol pa r a m e t er min typ. max unit v dd power supply voltage 2.7 3.0 3.3 v v ss ground 0 - 0 v ih input high voltage 2.2 - v cc + 0.2 ( note 1 ) v il input low voltage -0.2 ( note 2 ) - +0.6
110 psram type 3 psram_type03_06a0 february 25, 2004 advance information ac characteristics ta b l e 3 1 . dc characteristics (t a = -25 c to 85 c, vdd = 2.6 to 3.3v) symbol pa r a m e t er test condition min max unit i il input leakage current v in = v ss to v dd -1 1 a i lo output leakage current v io = v ss to v dd ce1# = v ih , ce2 = v il or oe# = v ih or we# = v il -1 1 a i cc1 operating current @ min. cycle time cycle time = min., 100% duty, i io = 0ma, ce1# = v il , ce2 = v ih , v in = v ih or v il - 35 ma i cc2 operating current @ max cycle time cycle time = 1 s, 100% duty i io = 0ma, ce1# 0.2v, ce2 v dd -0.2v, v in 0.2v or v in v dd -0.2v - 5 ma i sb1 standby current (cmos) ce1# = v dd ? 0.2v and ce2 = v dd ? 0.2v, other inputs = v ss ~ v cc - 100 a i sbd deep power-down ce2 0.2v, other inputs = v ss ~ v cc 10 a v ol output low voltage i ol = 2.1ma - 0.4 v v oh output high voltage i oh = -1.0ma 2.4 - v ta b l e 3 2 . ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) cycle symbol parameter 70 unit min max read t rc read cycle time 70 - ns t aa address access time - 70 ns t co1 chip enable (ce#1) access time - 70 ns t co2 chip enable (ce2) access time - 70 ns t oe output enable access time - 35 ns t ba data byte control access time - 70 ns t lz chip enable low to output in low-z 10 - ns t olz output enable low to output in low-z 5 - ns t blz data byte control low to output in low-z 10 - ns t hz chip enable high to output in high-z - 25 ns t ohz output enable high to output in high-z - 25 ns t bhz data byte control high to output in high-z - 25 ns t oh output data hold time 10 - ns
february 25, 2004 psram_type03_06a0 psram type 3 111 advance information write t wc write cycle time 70 - ns t wp write pulse width 50 - ns t aw address valid to end of write 60 - ns t cw chip enable to end of write 60 - ns t bw data byte control to end of write 60 - ns t as address set-up time 0 - ns t wr write recovery time 0 - ns t wzh we# low to output high-z - 20 ns t ow we# high to output in high-z 5 - ns t dw data to write overlap 35 - ns t dh data hold time 0 - ns t weh we# high time 5 10 ns ta b l e 3 3 . ac test conditions parameter condition output load 50 pf + 1 ttl gate input pulse level 0.4 v, 2.4 timing measurements 0.5 v cc t r , t f 5 ns note: including scope and jig capacitance figure 33. ac test loads table 32. ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) (continued) cycle symbol parameter 70 unit min max c l r l = 50 ? z 0 = 50 ? d out v l = 1.5 v = 50 pf (see note)
112 psram type 3 psram_type03_06a0 february 25, 2004 advance information timing diagrams figure 34. state diagram ta b l e 3 4 . standby mode characteristics power mode memory cell data standby current (a) wait time (s) standby valid 100 0 deep power down invalid 10 200 note: ce1# = oe# = v il , ce2 = we# = v ih , ub# and/or lb# = v il figure 35. read cycle 1?addressed controlled ce2=vih ce2=v il ce1# = v ih or v il , ce2=v ih ce2=v il ce2=v ih , ce1# =v ih or ub#, lb# =v ih ce1# =v il , ce2=v ih , ub# & lb# or/and lb# = v il powe r on initial state (wait 200 s) e deep powe r down mode standby mode powe r up sequence deep pow er down exit sequence active deep power down entry sequence t rc t oh t oh previous data valid data valid t a a address data out
february 25, 2004 psram_type03_06a0 psram type 3 113 advance information note: ce2 = we# = v ih figure 36. read cycle 2?cs1# controlled notes: 1. ce2 = v ih 2. ce2 = we# = v ih figure 37. write cycle 1?we# controlled t rc t oh t a a t olz high-z t ohz t bhz t hz data valid high-z address ce1# ub#, lb# oe# data out t lz t co t ba t blz t oe t wc t wr t aw t wp high-z high-z data valid t dh data undefined t dw t ow t whz address ce1# ub#, lb# we# data in data out t cw t bw t as
114 psram type 3 psram_type03_06a0 february 25, 2004 advance information notes: 1. ce2 = v ih 2. ce2 = we# = v ih figure 38. write cycle 2?cs1# controlled notes: 1. ce2 = v ih 2. ce2 = we# = v ih figure 39. write cycle3?ub#, lb# controlled t wc t aw data valid t dh t dw address ce1# ub#, lb# we# data in high-z data out t as t cw t wr t bw t wp t wc twr t aw t wp data valid t dh t dw address ce1# ub#, lb# we# data in high-z data out t cw t bw t as
february 25, 2004 psram_type03_06a0 psram type 3 115 advance information figure 40. deep power-down mode figure 41. power-up mode note: the s71jl064ha0 model 61 has a timing that is not supported at read operation. data will be lost if your system has multiple invalid address signal shorter than t rc during over 15 s at the read operation shown above. figure 42. abnormal timing normal operation normal operation 1 s suspend ~ ~ ~ ~ wake up deep power down mode 200 s ce2 mode ce1# ~ ~ 200 s v cc ce2 ce1# < t rc ce1# we# address > 15 s
116 psram type 4 psram_type04_18a0 august 30, 2004 advance information psram type 4 4 mbit (256k x 16) features ? wide voltage range: 2.7v to 3.3v ? typical active current: 3 ma @ f = 1 mhz ? low standby power ? automatic power-down when deselected functional description the type 4 psram is a high-performance cmos pseudo static ram (psram) or - ganized as 256k words by 16 bits that supports an asynchronous memory interface. this device features advanced circuit design to provide ultra-low active current. the device can be put into standby mode reducing power consumption dramatically when deselected (ce1# low, ce2 high or both bhe# and ble# are high). the input/output pins (i/o0 through i/o15) are placed in a high-imped - ance state when: deselected (ce1# high, ce2 low, oe# is deasserted high), or during a write operation (chip enabled and write enable we# low). reading from the device is accomplished by asserting the chip enables (ce1# low and ce2 high) and output enable (oe#) low while forcing the write enable (we#) high. if byte low enable (ble#) is low, then data from the memory location specified by the address pins will appear on i/o0 to i/o7. if byte high enable (bhe#) is low, then data from memory will appear on i/o8 to i/o15. see ta b l e 3 7 for a complete description of read and write modes. product portfolio notes: 1. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc (typ) and t a = 25c. v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby (i sb2 ) (a) f = 1 mhz f = f max min ty p max ty p . ( n o t e 1 ) max ty p . ( n o t e 1 ) max ty p . ( n o t e 1 ) max 2.7v 3.0v 3.3v 70 ns 3 5 tbd 25 ma 15 40
august 30, 2004 psram_type04_18a0 psram type 4 117 advance information maximum ratings (above which the useful life may be impaired. for user guidelines, not tested) storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . -40c to +85c supply voltage to ground potential . . . . . . . . . . . . . . . . . . . . . -0.4v to 4.6v dc voltage applied to outputs in high-z state (note 1, 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 3.7v dc input voltage (note 1, 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 3.7v output current into outputs (low). . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma static discharge voltage . . . . . . . . . >2001v (per mil-std-883, method 3015) latch-up current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 ma notes: 1. v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 2. v il(min) = ?0.5v for pulse durations less than 20 ns. 3. overshoot and undershoot specifications are characterized and are not 100% tested. operating range ta b l e 3 5 . dc electrical characteristics (over the operating range) notes: 1. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. ambient temperature (t a ) v cc -25c to +85c 2.7v to 3.3v parameter description test conditions min. typ. (note 1) max unit v cc supply voltage 2.7 3.3 v v oh output high voltage i oh = ?1.0 ma v cc - 0.4 v ol output low voltage i ol = 0.1 ma 0.4 v ih input high voltage 0.8 * v cc v cc + 0.4 v il input low voltage f = 0 -0.4 0.4 i ix input leakage current gnd v in v cc -1 +1 a i oz output leakage current gnd v out v cc , output disabled -1 +1 i cc v cc operating supply current f = f max = 1/t rc v cc = 3.3v i out = 0 ma cmos levels tbd 15 ma f = 1 mhz 3 i sb1 automatic ce# power-down current?cmos inputs ce# v cc ? 0.2v, ce2 0.2v v in v cc ? 0.2v, v in 0.2v, f = f max (address and data only), f=0 (oe#, we#, bhe# and ble#) 250 a i sb2 automatic ce# power-down current?cmos inputs ce# v cc ? 0.2v, ce2 0.2v v in v cc ? 0.2v or v in 0.2v, f = 0, v cc = 3.3v 40
118 psram type 4 psram_type04_18a0 august 30, 2004 advance information capacitance note: tested initially and after any design or process changes that may affect these parameters. thermal resistance note: tested initially and after any design or process changes that may affect these parameters. ac test loads and waveforms parameter description test condition max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ.) 8 pf c out output capacitance 8 parameter description test conditions vfbga unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 55 c/w jc thermal resistance (junction to case) 17 figure 43. ac test loads and waveforms parameters 3.0v v cc unit r1 22000 ? r2 22000 r th 11000 v th 1.50 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 rise time: 1 v/ns fall time: 1 v/ns
august 30, 2004 psram_type04_18a0 psram type 4 119 advance information ta b l e 3 6 . switching characteristics notes: 1. test conditions assume signal transition time of 1v/ns or higher, timing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh and 30 pf load capacitance. 2. t hzoe , t hzce , t hzbe and t hzwe transitions are measured when the outputs enter a high-impedance state. 3. high-z and low-z parameters are characterized and are not 100% tested. 4. to achieve 55-ns performance, the read access should be ce# controlled. in this case t ace is the critical parameter and t sk is satisfied when the addresses are stable prior to chip enable going active. for the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. 5. the internal write time of the memory is defined by the overlap of we#, ce#1 = v il , ce2 = v ih , b he and/or b le =v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set - up and hold timing should be referenced to the edge of the signal that terminates write. parameter description min max unit read cycle t rc read cycle time 70 ns t aa address to data valid 70 t oha data hold from address change 10 t ace ce#1 low and ce2 high to data valid 70 t doe oe# low to data valid 35 t lzoe oe# low to low z (note 2, 3) 5 t hzoe oe# high to high z (note 2, 3) 25 t lzce ce#1 low and ce2 high to low z (note 2, 3) 5 t hzce ce#1 high and ce2 low to high z (note 2, 3) 25 t dbe bhe# / ble# low to data valid 70 t lzbe bhe# / ble# low to low z (note 2, 3) 5 t hzbe bhe# / ble# high to high z (note 2, 3) 25 t sk (note 4) address skew 10 write cycle (note 5) t wc write cycle time 70 ns t sce ce#1 low an ce2 high to write end 55 t aw address set-up to write end 55 t ha address hold from write end 0 t sa address set-up to write start 0 t pwe we# pulse width 55 t bw ble# / bhe# low to write end 55 t sd data set-up to write end 25 t hd data hold from write end 0 t hzwe we# low to high z (note 2, 3) 25 t lzwe we# high to low z (note 2, 3) 5
120 psram type 4 psram_type04_18a0 august 30, 2004 advance information switching waveforms notes: 1. to achieve 55-ns performance, the read access should be ce# controlled. in this case t ace is the critical parameter and t sk is satisfied when the addresses are stable prior to chip enable going active. for the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. 2. device is continuously selected. oe#, ce# = v il . 3. we# is high for read cycle. notes: 1. to achieve 55-ns performance, the read access should be ce# controlled. in this case t ace is the critical parameter and t sk is satisfied when the addresses are stable prior to chip enable going active. for the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. 2. we# is high for read cycle. figure 44. read cycle 1 (address transition controlled) figure 45. read cycle 2 (oe# controlled) address data out previous d ata valid data valid t rc t aa t oha t sk data valid t rc t ace t doe t lzoe t lzce high impedence t hzoe high impedence address ce 2 t hzbe t lzbe t hzce data out t dbe t sk ce#1 bhe#/ble# oe#
august 30, 2004 psram_type04_18a0 psram type 4 121 advance information notes: 1. high-z and low-z parameters are characterized and are not 100% tested. 2. the internal write time of the memory is defined by the overlap of we#, ce#1 = v il , ce2 = v ih , b he and/or b le =v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set - up and hold timing should be referenced to the edge of the signal that terminates write. 3. data i/o is high impedance if oe# v ih . 4. if chip enable goes inactive simultaneously with we# = high, the output remains in a high-impedance state. 5. during the don?t care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. figure 46. write cycle 1 (we# controlled)
122 psram type 4 psram_type04_18a0 august 30, 2004 advance information notes: 1. high-z and low-z parameters are characterized and are not 100% tested. 2. the internal write time of the memory is defined by the overlap of we#, ce#1 = v il , ce2 = v ih , b he and/or b le =v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set - up and hold timing should be referenced to the edge of the signal that terminates write. 3. data i/o is high impedance if oe# v ih . 4. if chip enable goes inactive simultaneously with we# = high, the output remains in a high-impedance state. 5. during the don?t care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. figure 47. write cycle 2 (ce#1 or ce2 controlled) t hd t sd t pwe t ha t aw t sce t wc t hzoe address ce 2 data i/o don?t care t bw t sa valid data ce#1 we# bhe#/ble# oe#
august 30, 2004 psram_type04_18a0 psram type 4 123 advance information notes: 1. if chip enable goes inactive simultaneously with we# = high, the output remains in a high-impedance state. 2. during the don?t care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. notes: 1. if chip enable goes inactive simultaneously with we# = high, the output remains in a high-impedance state. 2. during the don?t care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. figure 48. write cycle 3 (we# controlled, oe# low) figure 49. write cycle 4 (bhe#/ble# controlled, oe# low) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce 2 data i/o t bw don?t care ce#1 bhe#/ble# we# ce#1 ce2 bhe#/ble# we#
124 psram type 4 psram_type04_18a0 august 30, 2004 advance information truth table ta b l e 3 7 . truth table ce#1 ce2 we# oe# bhe# ble# inputs / outputs mode power hxxxxxhigh-z deselect/power-down standby (i sb ) xlxxxxhigh-z xxxxhhhigh-z l h h l l l data out (i/o0?i/o15) read (upper byte and lower byte) active (i cc ) lhhlhl data out (i/o0 ?i/o7); i/o8?i/o15 in high z read (upper byte only) lhhllh data out (i/o8?i/o15); i/o0?i/o7 in high z read (lower byte only) l h h h l l high-z output disabled l h h h h l high-z output disabled lhhhlhhigh-z output disabled l h l x l l data in (i/o0?i/o15) write (upper byte and lower byte) lhlxhl data in (i/o0?i/o7); i/o8?i/o15 in high z write (lower byte only) lhlxlh data in (i/o8?i/o15); i/o0 ?i/o7 in high z write (upper byte only)
april 26, 2004 psram_type06_14_a0 psram type 6 125 advance information psram type 6 2m word by 16-bit cmos pseudo static ram (32m density) 4m word by 16-bit cmos pseu do static ram (64m density) features ? single power supply voltage of 2.6 to 3.3 v ? direct ttl compatibility for all inputs and outputs ? deep power-down mode: memory cell data invalid ? page operation mode: ? page read operation by 8 words ? logic compatible with sram r/w () pin ? standby current ? standby = 70 a (32m) ? standby = 100 a (64m) ? deep power-down standby = 5 a ? access times pin description 32m 64m access time 70 ns ce1# access time 70 ns oe# access time 25 ns page access time 30 ns pin name description a 0 to a 21 address inputs a0 to a2 page address inputs i/o1 to i/o16 data inputs/outputs ce1# chip enable input ce2 chip select input we# write enable input oe# output enable input lb#,ub# data byte control inputs v dd power supply gnd ground nc not connection
126 psram type 6 psram_type06_14_a0 april 26, 2004 advance information functional description legend: l = low-level input (v il ), h = high-level input (v ih ), x = v il or v ih , high-z = high impedance. absolute maximum ratings dc recommended operating conditions (ta = -40c to 85c) note: v ih (max) v dd = 1.0 v with 10 ns pulse width. v il (min) -1.0 v with 10 ns pulse width. mode ce1# ce2 oe# we# lb# ub# address i/o 1-8 i/o 9-16 power read (word) l h l h l l x d out d out i ddo read (lower byte) l h l h l h x d out high-z i ddo read (upper byte) l h l h h l x high-z d out i ddo write (word) l h x l l l x d in d in i ddo write (lower byte) lhx l lhx d in invalid i ddo write (upper byte) l h x l h l x invalid d in i ddo outputs disabled l h h h x x x high-z high-z i ddo standby h h x x x x x high-z high-z i ddo deep power-down standby h l x x x x x high-z high-z i ddsd symbol rating value unit v dd power supply voltage -1.0 to 3.6 v v in input voltage -1.0 to 3.6 v v out output voltage -1.0 to 3.6 v t opr operating temperature -40 to 85 c t strg storage temperature -55 to 150 c p d power dissipation 0.6 w i out short circuit output current 50 ma symbol parameter min ty p max unit v dd power supply voltage 2.6 2.75 3.3 v v ih input high voltage 2.0 ? v dd + 0.3 (note) v il input low voltage -0.3 (note) ? 0.4
april 26, 2004 psram_type06_14_a0 psram type 6 127 advance information dc characteristics (ta = -40c to 85c, vdd = 2.6 to 3.3 v) (see note 3 to 4) capacitance (ta = 25c, f = 1 mhz) note: this parameter is sampled periodically and is not 100% tested. ac characteristics and operating conditions (ta = -40c to 85c, vdd = 2.6 to 3.3 v) (see note 5 to 11) symbol parameter test condition min ty p . max unit i il input leakage current v in = 0 v to v dd -1.0 ? +1.0 a i lo output leakage current output disable, v out = 0 v to v dd -1.0 ? +1.0 a v oh output high voltage i oh = - 0.5 ma 2.0 ? v v v ol output low voltage i ol = 1.0 ma ? ? 0.4 v i ddo1 operating current ce1#= v il , ce2 = v ih , i out = 0 ma, t rc = min et5uz8a-43ds ? ? 40 ma et5vb5a-43ds ? ? 50 i ddo2 page access operating current ce1#= v il , ce2 = v ih , i out = 0 ma page add. cycling, t rc = min ? ? 25 ma i dds standby current(mos) ce1# = v dd - 0.2 v, ce2 = v dd - 0.2 v et5uz8a-43ds ? ? 70 ma et5vb5a-43ds ? ? 100 a i ddsd deep power-down standby current ce2 = 0.2 v ? ? 5 a symbol parameter test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf symbol parameter min max unit t rc read cycle time 70 10000 ns t acc address access time ? 70 ns t co chip enable (ce1#) access time ? 70 ns t oe output enable access time ? 25 ns t ba data byte control access time ? 25 ns t coe chip enable low to output active 10 ? ns t oee output enable low to output active 0 ? ns t be data byte control low to output active 0 ? ns t od chip enable high to output high-z ? 20 ns t odo output enable high to output high-z ? 20 ns t bd data byte control high to output high-z ? 20 ns
128 psram type 6 psram_type06_14_a0 april 26, 2004 advance information ac test conditions t oh output data hold time 10 ? ns t pm page mode time 70 10000 ns t pc page mode cycle time 30 ? ns t aa page mode address access time ? 30 ns t aoh page mode output data hold time 10 ? ns t wc write cycle time 70 10000 ns t wp write pulse width 50 ? ns t cw chip enable to end of write 70 ? ns t bw data byte control to end of write 60 ? ns t aw address valid to end of write 60 ? ns t as address set-up time 0 ? ns t wr write recovery time 0 ? ns t ceh chip enable high pulse width 10 ? ns t weh write enable high pulse width 6 ? ns t odw we# low to output high-z ? 20 ns t oew we# high to output active 0 ns t ds data set-up time 30 ? ns t dh data hold time 0 ? ns t cs ce2 set-up time 0 ? ns t ch ce2 hold time 300 ? s t dpd ce2 pulse width 10 ? ms t chc ce2 hold from ce1# 0 ? ns t chp ce2 hold from power on 30 ? s parameter condition output load 30 pf + 1 ttl gate input pulse level v dd - 0.2 v, 0.2 v timing measurements v dd x 0.5 reference level v dd x 0.5 t r , t f 5 ns symbol parameter min max unit
april 26, 2004 psram_type06_14_a0 psram type 6 129 advance information timing diagrams read timings figure 50. read cycle t acc t od t oh valid data out t oe t be t oee t bd hi-z hi-z t co fix-h t ba t coe indeterminate t odo t rc address a0 to a20(32m) a0 to a21(64m) ce1# ce2 oe# we# ub# , lb# d out i/o1 to i/o16
130 psram type 6 psram_type06_14_a0 april 26, 2004 advance information figure 51. page read cycle (8 words access) t pm t pc t rc t aoh fix-h hi-z hi-z t be d out t acc t coe t co t oe t ba t oee t pc t aoh t pc d out t od t oh t bd t odo t aa * maximum 8 words d out t aoh d out t aa t aa address a0 to a2 address a 3 to a20(32m) a 3 to a21(64m) ce1# ce2 oe# we# ub#, lb# d out i/o1 to i/o16
april 26, 2004 psram_type06_14_a0 psram type 6 131 advance information write timings figure 52. write cycle #1 (we# controlled) (see note 8) ub# d in i/o1 to i/o16 d out i/o1 to i/o16 ce2 ce1# we# address a 0 to a20 a 0 to (32m) a21(64m) t wc t as t bw t wr valid data in t odw t wp t ds t dh t oew (see note 11) (s ) ee note 10 hi-z t cw t wr t weh t aw t wr t ch (see note 9) (see note 9) , lb#
132 psram type 6 psram_type06_14_a0 april 26, 2004 advance information deep power-down timing power-on timing figure 53. write cycle #2 (ce# controlled) (see note 8) figure 54. deep power down timing figure 55. power-on timing t wc t wp t as t cw t wr valid data in t odw t ds t dh t coe hi-z hi-z t aw t wr t ceh t bw t be t wr t ch (see note 9) address a0 to a20 a0 to (32m) a21(64m) we# ce1# ce2 ub#, lb# d out i/o1 to i/o16 d in i/o1 to i/o16 t cs t dpd t ch ce1# ce2 t chc t chp t ch v dd min v dd ce1# ce2
april 26, 2004 psram_type06_14_a0 psram type 6 133 advance information provisions of address skew read in case multiple invalid address cycles shorter than t rc min sustain over 10 s in an active status, at least one valid address cycle over t rc min is required during 10s. write in case multiple invalid address cycles shorter than t wc min sustain over 10 s in an active status, at least one valid address cycle over t wc min is required during 10 s. notes: 1. stresses greater than listed under " absolute maximum ratings " section may cause permanent damage to the device. 2. all voltages are reference to gnd. 3. i ddo depends on the cycle time. 4. i ddo depends on output loading. specified values are defined with the output open condition. 5. ac measurements are assumed t r , t f = 5 ns. 6. parameters t od , t odo , t bd and t od w define the time at which the output goes the open condition and are not output voltage reference levels. 7. data cannot be retained at deep power-down stand-by mode. 8. if oe# is high during the write cycle, the outputs will remain at high impedance. 9. during the output state of i/o signals, input signals of reverse polarity must not be applied. 10. if ce1# or lb#/ub# goes low coincident with or after we# goes low, the outputs will remain at high impedance. 11. if ce1# or lb#/ub# goes high coincident with or before we# goes high, the outputs will remain at high impedance. figure 56. read figure 57. write over 10 s t rc min ce1# we# a ddress t wp min t wc min ce1# we# a ddress
134 psram type 7 psram_type07_13_a1 november 2, 2004 advance information psram type 7 cmos 1m/2m/4m-word x 16-bit fast cycle random access memory with low power sram interface 16mb (1m word x 16-bit) 32mb (2m word x 16-bit) 64mb (4m word x 16-bit) features ? asynchronous sram interface ? fast access time ? tce = taa = 60ns max (16m) ? tce = taa = 65ns max (32m/64m) ? 8 words page access capability ? tpaa = 20ns max (32m/64m) ? low voltage operating condition ? vdd = +2.7v to +3.1v ? wide operating temperature ? ta = -30c to +85c ? byte control by lb and ub ? various power down modes ? sleep (16m) ? sleep, 4m-bit partial, or 8m-bit partial (32m) ? sleep, 8m-bit partial, or 16m-bit partial (64m) pin description pin name description a 21 to a 0 address input: a 19 to a 0 for 16m, a 20 to a 0 for 32m, a 21 to a 0 for 64m ce1# chip enable (low active) ce2# chip enable (high active) we# write enable (low active) oe# output enable (low active) ub# upper byte control (low active) lb# lower byte control (low active) dq 16 - 9 upper byte data input/output dq 8 - 1 lower byte data input/output v dd power supply v ss ground
november 2, 2004 psram_type07_13_a1 psram type 7 135 advance information functional description legend: l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance. notes: 1. should not be kept this logic condition longer than 1 ms. please contact local spansion representative for the relaxation of 1ms limitation. 2. power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of the power-down program, 16m has data retentio n in all modes except power down. refer to power down for details. 3. can be either v il or v ih but must be valid before read or write. power down (for 32m, 64m only) power down the power down is a low-power idle state controlled by ce2. ce2 low drives the device in power-down mode and maintain s the low-power idle state as long as ce2 is kept low. ce2 high resumes the device from power-down mode. these devices have three power-down modes. these can be programmed by series of read/write operation. each mode has following features. the default state is sleep and it is the lowest power consumption but all data is lost once ce2 is brought to low for power down. it is not required to program to sleep mode after power-up. mode ce2# ce1# we# oe# lb# ub# a 21-0 dq 8-1 dq 16-9 standby (deselect) h h x x x x x high-z high-z output disable (note 1) hl h h x x note 3 high-z high-z output disable (no read) hl h h valid high-z high-z read (upper byte) h l valid high-z output valid read (lower byte) l h valid output valid high-z read (word) l l valid output valid output valid no write lh h h valid invalid invalid write (upper byte) h l valid invalid input valid write (lower byte) l h valid input valid invalid write (word) l l valid input valid input valid power down lxxxxx x high-z high-z 32m 64m mode retention data retention address mode retention data retention address sleep (default) no n/a sleep (default) no n/a 4m partial 4m bit 00000h to 3ffffh 8m partial 8m bit 00000h to 7ffffh 8m partial 8m bit 00000h to 7ffffh 16m partial 16m bit 00000h to fffffh
136 psram type 7 psram_type07_13_a1 november 2, 2004 advance information power down program sequence the program requires 6 read/write operations with a unique address. between each read/write operation requires that device be in standby mode. the following table shows the detail sequence. the first cycle reads from the most significant address (msb). the second and third cycle are to write back the data (rda) read by first cycle. if the second or third cycle is written in to the different address, the program is cancelled, and the data written by the second or third cycle is valid as a normal write operation. the fourth and fifth cycles write to msb. th e data from the fourth and fifth cycles is ?don?t care.? if the fourth or fifth cy cles are written into different address, the program is also cancelled but write data might not be written as normal write operation. the last cycle is to read from specific address key for mode selection. once this program sequence is performed from a partial mode to the other partial mode, the written data stored in memory ce ll array can be lost. so, it should per - form this program prior to regular read/write operation if partial mode is used. address key the address key has following format. cycle # operation address data 1st read 3fffffh (msb) read data (rda) 2nd write 3fffffh rda 3rd write 3fffffh rda 4th write 3fffffh don?t care (x) 5th write 3fffffh x 6th read address key read data (rdb) mode address 32m 64m a21 a20 a19 a18 - a0 binary sleep (default) sleep (default) 1 1 1 1 3fffffh 4m partial n/a 1 1 0 1 37ffffh 8m partial 8m partial 1 0 1 1 2fffffh n/a 16m partial 1 0 0 1 27ffffh
november 2, 2004 psram_type07_13_a1 psram type 7 137 advance information absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating cond itions (see warning below) notes: 1. maximum dc voltage on input and i/o pins is v dd +0.2v. during voltage transitions, inputs can positive overshoot to v dd +1.0v for periods of up to 5 ns. 2. minimum dc voltage on input or i/o pins is -0.3v. during voltage transitions, inputs can negative overshoot v ss to -1.0v for periods of up to 5ns. warning: recommended operating conditions are normal operat ing ranges for the semiconductor device. all the de- vice?s electrical characteristics are warra nted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges can adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating cond itions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fu jitsu representative before- hand. package capacitance test conditions: t a = 25c, f = 1.0 mhz item symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage at any pin relative to v ss v in , v out -0.5 to +3.6 v short circuit output current i out 50 ma storage temperature t stg -55 to +125 c parameter symbol min max unit supply voltage v dd 2.7 3.1 v v ss 0 0 v high level input voltage (note 1) v ih v dd 0.8 v dd +0.2 v high level input voltage (note 1) v il -0.3 v dd 0.2 v ambient temperature t a -30 85 c symbol description te s t s e t u p ty p max unit c in1 address input capacitance v in = 0v ? 5 pf c in2 control input capacitance v in = 0v ? 5 pf c io data input/output capacitance v io = 0v ? 8 pf
138 psram type 7 psram_type07_13_a1 november 2, 2004 advance information dc characteristics (under recommended conditions unless otherwise noted) notes: 1. all voltages are referenced to v ss . 2. dc characteristics are measured after following power-up timing. 3. i out depends on the output load conditions. parameter symbol test conditions 16m 32m 64m unit min. max. min. max. min. max. input leakage current i li v in = v ss to v dd -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 a output leakage current i lo v out = v ss to v dd , output disable -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 a output high voltage level v oh v dd = v dd (min), i oh = ?0.5ma 2.2 ? 2.4 ? 2.4 ? v output low voltage level v ol i ol = 1ma ? 0.4 ? 0.4 ? 0.4 v v dd power down current i ddps v dd = v dd max., v in = v ih or v il , ce2 0.2 v sleep 10 ? 10 ? 10 a i ddp4 4m partial n/a ? 40 n/a a i ddp8 8m partial n/a ? 50 ? 80 a i ddp16 16m partial n/a n/a ? 100 a v dd standby current i dds v dd = v dd max., v in = v ih or v il ce 1 = ce2 = v ih ? 1 ? 1.5 ? 1.5 ma i dds1 v dd = v dd max., v in 0.2v or v in v dd ? 0.2v, ce 1 = ce2 v dd ? 0.2v ta< + 85 c ? 100 ? 80 ? 170 a ta< + 40 c 90 a v dd active current i dda1 v dd = v dd max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma t rc / t wc = min. ? 20 ? 30 ? 40 ma i dda2 t rc / t wc = 1 s ? 3 ? 3 ? 5 ma v dd page read current i dda3 v dd = v dd max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma, t prc = min. n/a ? 10 ? 10 ma
november 2, 2004 psram_type07_13_a1 psram type 7 139 advance information ac characteristics (under recommended operating co nditions unless otherwise noted) read operation notes: 1. maximum value is applicable if ce#1 is kept at low without change of address input of a3 to a21. if needed by system operation, please contact local spansion representative for the relaxation of 1s limitation. 2. address should not be changed within minimum t rc . 3. the output load 50 pf with 50 ohm termination to v dd x 0.5 (16m), the output load 50 pf (32m and 64m). 4. the output load 5pf. 5. applicable to a3 to a21 (32m and 64m) when ce1# is kept at low. 6. applicable only to a0, a1 and a2 (32m and 64m) when ce1# is kept at low for the page address access. 7. in case page read cycle is continued with keeping ce1# stays low, ce1# must be brought to high within 4 s. in other words, page read cycle must be closed within 4 s. 8. applicable when at least two of address inputs among applicable are switched from previous state. 9. t rc (min) and t prc (min) must be satisfied. 10. if actual value of t whol is shorter than specified minimum values, the actual t aa of following read can become longer by the amount of subtracting the actual value from the specified minimum value. parameter symbol 16m 32m 64m unit notes min. max. min. max. min. max. read cycle time t rc 70 1000 65 1000 65 1000 ns 1, 2 ce1# access time t ce ?60?65?65ns3 oe# access time t oe ?40?40?40ns3 address access time t aa ?60?65?65ns3, 5 lb# / ub# access time t ba ?30?30?30ns3 page address access time t paa n/a ? 20 ? 20 ns 3,6 page read cycle time t prc n/a 20 1000 20 1000 ns 1, 6, 7 output data hold time t oh 5?5?5?ns3 ce1# low to output low-z t clz 5?5?5?ns4 oe# low to output low-z t olz 0?0?0?ns4 lb# / ub# low to output low-z t blz 0?0?0?ns4 ce1# high to output high-z t chz ?20?20?20ns3 oe# high to output high-z t ohz ?20?14?14ns3 lb# / ub# high to output high-z t bhz ?20?20?20ns3 address setup time to ce1# low t asc ? 6??6??6?ns address setup time to oe# low t aso 10 ? 10 ? 10 ? ns address invalid time t ax ?10?10?10ns5, 8 address hold time from ce1# high t chah -6 ? ?6 ? ?6 ? ns 9 address hold time from oe# high t ohah -6 ? ?6 ? ?6 ? ns we# high to oe# low time for read t whol 10 1000 12 ? 25 ? ns 10 ce1# high pulse width t cp 10 ? 12 ? 12 ? ns
140 psram type 7 psram_type07_13_a1 november 2, 2004 advance information ac characteristics write operation notes: 1. maximum value is applicable if ce1# is kept at low without any address change. if the relaxation is needed by system operation, please contact local spansion representative for the relaxation of 1s limitation. 2. minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wr ). 3. write pulse is defined from high to low transition of ce1#, we#, or lb#/ub#, whichever occurs last. 4. applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce1# or we# whichever occurs last. 5. applicable for byte mask only. byte mask hold time is defined from the low to high transition of ce1# or we# whichever occurs first. 6. write recovery is defined from low to high transition of ce1#, we#, or lb#/ub#, whichever occurs first. 7. t wph minimum is absolute minimum value for device to detect high level. and it is defined at minimum v ih level. 8. if oe# is low after minimum t ohcl , read cycle is initiated. in other words, oe# must be brought to high within 5ns after ce1# is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met. 9. if oe# is low after new address input, read cycle is initiated. in other word, oe# must be brought to high at the same time or before new address valid. once read cycle is init iated, new write pulse should be input after minimum t rc is met and data bus is in high-z. parameter symbol 16m 32m 64m unit notes min. max. min. max. min. max. write cycle time t wc 70 1000 65 1000 65 1000 ns 1,2 address setup time t as 0?0?0?ns3 ce1# write pulse width t cw 45 ? 40 ? 40 ? ns 3 we# write pulse width t wp 45 ? 40 ? 40 ? ns 3 lb#/ub# write pulse width t bw 45 ? 40 ? 40 ? ns 3 lb#/ub# byte mask setup time t bs -5 ? ?5 ? ?5 ? ns 4 lb#/ub# byte mask hold time t bh -5 ? ?5 ? ?5 ? ns 5 write recovery time t wr 0?0?0?ns6 ce1# high pulse width t cp 10 ? 12 ? 12 ? ns we# high pulse width t whp 7.5 1000 7.5 1000 7.5 1000 ns 7 lb#/ub# high pulse width t bhp 10 1000 12 1000 12 1000 ns data setup time t ds 15 ? 12 ? 12 ? ns data hold time t dh 0?0?0?ns oe# high to ce1# low setup time for write t ohcl -5 ? ?5 ? ?5 ? ns 8 oe# high to address setup time for write t oes 0?0?0?ns9 lb# and ub# write pulse overlap t bwo 30 ? 30 ? 30 ? ns
november 2, 2004 psram_type07_13_a1 psram type 7 141 advance information ac characteristics power down parameters notes: 1. applicable also to power-up. 2. applicable when 4mb and 8mb partial modes are programmed. other timing parameters notes: 1. some data might be written into any address location if t chwx (min) is not satisfied. 2. the input transition time (t t ) at ac testing is 5ns as shown in below. if actual tt is longer than 5ns, it can violate the ac specification of some of the timing parameters. parameter symbol 16m 32m 64m unit note min. max. min. max. min. max. ce2 low setup time for power down entry t csp 10 ? 10 ? 10 ? ns ce2 low hold time after power down entry t c2lp 80 ? 65 ? 65 ? ns ce1# high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? 300 ? 300 ? s 1 ce1# high hold time following ce2 high after power down exit [not in sleep mode] t chhp n/a 1 ? 1 ? s 2 ce1# high setup time following ce2 high after power down exit t chs 0 ? 0 ? 0 ? ns 1 parameter symbol 16m 32m 64m unit note min. max. min. max. min. max. ce1# high to oe# invalid time for standby entry t chox 10 ? 10 ? 10 ? ns ce1# high to we# invalid time for standby entry t chwx 10 ? 10 ? 10 ? ns 1 ce2 low hold time after power-up t c2lh 50 ? 50 ? 50 ? s ce1# high hold time following ce2 high after power-up t chh 300 ? 300 ? 300 ? s input transition time t t 1 25 1 25 1 25 ns 2
142 psram type 7 psram_type07_13_a1 november 2, 2004 advance information ac characteristics ac test conditions ac measurement output load circuits figure 58. ac output load circuit ? 16 mb figure 59. ac output load circuit ? 32 mb and 64 mb symbol description te s t s e t u p value unit note v ih input high level v dd * 0.8 v v il input low level v dd * 0.2 v v ref input timing measurement level v dd * 0.5 v t t input transition time between v il and v ih 5 ns device under test v dd v dd *0.5 v v ss out 0.1 f 50 pf 50 ohm device under test v dd v ss out 0.1 f 50pf
november 2, 2004 psram_type07_13_a1 psram type 7 143 advance information timing diagrams read timings note: this timing diagram assumes ce2=h and we#=h. figure 60. read timing #1 (basic timing) note: this timing diagram assumes ce2=h and we#=h. figure 61. read timing #2 (oe# address access t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz lb#/ ub# t oe t ba t blz t clz t aa valid data output address ce 1# dq (output) t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso lb#/ub#
144 psram type 7 psram_type07_13_a1 november 2, 2004 advance information note: this timing diagram assumes ce2=h and we#=h. figure 62. read timing #3 (lb#/ub# byte access) note: this timing diagram assumes ce2=h and we#=h. figure 63. read timing #4 (page address access after ce1# control access for 32m and 64m only) t aa valid data output address dq1-8 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output ce1#, oe# valid data output (normal access) a ddress (a2-a0) ce1# dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa a ddress (a21-a3) address valid t paa t oh t prc t paa t prc t oh address valid address valid t rc t asc lb#/ub#
november 2, 2004 psram_type07_13_a1 psram type 7 145 advance information notes: 1. this timing diagram assumes ce2=h and we#=h. 2. either or both lb# and ub# must be low when both ce1# and oe# are low. figure 64. read timing #5 (random and page address access for 32m and 64m only) write timings note: this timing diagram assumes ce2=h. figure 65. write timing #1 (basic timing) valid data output (normal access) a ddress (a2-a0) ce 1# dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa a ddress (a21-a3) address valid t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso lb#/ub# t as valid data input a ddress ce1# dq (input) we# t dh t ds t wc t wr t wp t cw lb#, ub# t as t bw address valid t as t as t wr oe# t ohcl t as t as t wr t cp t whp t bhp
146 psram type 7 psram_type07_13_a1 november 2, 2004 advance information note: this timing diagram assumes ce2=h. figure 66. write timing #2 (we# control) note: this timing diagram assumes ce2=h and oe#=h. figure 67. write timing #3-1(we#/lb# /ub# byte write control) t as a ddress we# ce1# t wc t wr t wp lb#, ub# address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah t whp t as a ddress we# ce1# t wc t wr t wp lb# address valid t as t wr t wp valid data input dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp
november 2, 2004 psram_type07_13_a1 psram type 7 147 advance information note: this timing diagram assumes ce2=h and oe#=h. figure 68. write timing #3-3 (we#/lb#/ub# byte write control) note: this timing diagram assumes ce2=h and oe#=h. figure 69. write timing #3-4 (we#/lb#/ub# byte write control) t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t wr t bw t as t wr t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo t bhp t bhp
148 psram type 7 psram_type07_13_a1 november 2, 2004 advance information read/write timings notes: 1. this timing diagram assumes ce2=h. 2. write address is valid from either ce1# or we# of last falling edge. figure 70. read/write timing #1-1 (ce1# control) notes: 1. this timing diagram assumes ce2=h. 2. oe# can be fixed low during write operation if it is ce1# controlled write at read-write-read sequence. figure 71. read / write timing #1-2 (ce1#/we#/oe# control) read data output a ddress ce1# dq we# t wc t cw oe# t ohcl ub#, lb# t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t clz t oh read data output a ddress ce1# dq we# t wc t wp oe# t ohcl ub#, lb# t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output
november 2, 2004 psram_type07_13_a1 psram type 7 149 advance information notes: 1. this timing diagram assumes ce2=h. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 72. read / write timing #2 (oe#, we# control) notes: 1. this timing diagram assumes ce2=h. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 73. read / write timing #3 (oe#, we#, lb#, ub# control) read data output a ddress ce1# dq we# t wc t wp oe# ub#, lb# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah t whol read data output a ddress ce1# dq we# t wc t bw oe# ub#, lb# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes t whol t wr
150 psram type 7 psram_type07_13_a1 november 2, 2004 advance information note: the t c2lh specifies after v dd reaches specified minimum level. figure 74. power-up timing #1 note: the t chh specifies after v dd reaches specified minimum level and applicable to both ce1# and ce2. figure 75. power-up timing #2 note: this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power-down program was not performed prior to this reset. figure 76. power down entry and exit timing t c2lh ce1# v dd v dd min 0v ce2 t chh t chs ce1# v dd v dd min 0v ce2 t chh t csp ce1# power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z
november 2, 2004 psram_type07_13_a1 psram type 7 151 advance information note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce1# low to high transition. figure 77. standby entry timing after read or write notes: 1. the all address inputs must be high from cycle #1 to #5. 2. the address key must confirm the format specified in page 136. if not, the operation and data are not guaranteed. 3. after t cp following cycle #6, the power down program is completed and returned to the normal operation. figure 78. power down program timing (for 32m/64m only) t chox ce1# oe# we# active (read) standby active (write) standby t chwx address ce1# dq* 3 we# t rc oe# lb#, ub# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp t cp * 3 cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb
152 sram sram_type01_02a0 june 15, 2004 advance information sram 4/8 megabit cmos sram common features ? process technology: full cmos ? power supply voltage: 2.7~3.3v ? three state outputs notes: 1. ub#, lb# swapping is available only at x16. x8 or x16 select by byte# pin. pin description version density organization (i sb1 , max.) standby (i cc2 , max.) operating mode f 4mb x8 or x16 (note 1) 10 a 22 ma dual cs, ub# / lb# (tcs) g 4mb x8 or x16 (note 1) 10 a 22 ma dual cs, ub# / lb# (tcs) c 8mb x8 or x16 (note 1) 15 a 22 ma dual cs, ub# / lb# (tcs) d 8mb x16 tbd tbd dual cs, ub# / lb# (tcs) pin name description i/o cs1#, cs2 chip selects i oe# output enable i we# write enable i byte# word (v cc )/byte (v ss ) select i a0~a17 (4m) a0~a18 (8m) address inputs i sa address input for byte mode i i/o0~i/o15 data inputs/outputs i/o v cc power supply - v ss ground - dnu do not use - nc no connection -
june 15, 2004 sram_type01_02a0 sram 153 advance information functional description 4m version f, 4m version g, 8m version c note: x means don?t care (must be low or high state). byte mode cs1# cs2 oe# we# byte# sa lb# ub# io 0~7 io 8~15 mode power h x x x x x x x high-z high-z deselected standby x l x x x x x x high-z high-z deselected standby x x x x x x h h high-z high-z deselected standby l h h h v cc x l x high-z high-z output disabled active l h h h v cc x x l high-z high-z output disabled active l h l h v cc x l h d out high-z lower byte read active l h l h v cc x h l high-z d out upper byte read active l h l h v cc x l l d out d out word read active l h x l v cc x l h d in high-z lower byte write active l h x l v cc x h l high-z d in upper byte write active l h x l v cc x l l d in d in word write active cs1# cs2 oe# we# byte# sa lb# ub# io 0~7 io 8~15 mode power h x x x x x x x high-z high-z deselected standby x l x x x x x x high-z high-z deselected standby l h h h x x h h high-z high-z deselected standby l h l l v cc x l x high-z high-z output disabled active l h x l v cc x x l high-z high-z output disabled active
154 sram sram_type01_02a0 june 15, 2004 advance information functional description 8m version d note: x means don?t care (must be low or high state). absolute maximum ratings (4m version f) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability . absolute maximum ratings (4m version g, 8m version c, 8m version d) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability . cs1# cs2 oe# we# lb# ub# io 0~8 io 9~16 mode power h x x x x x high-z high-z deselected standby x l x x x x high-z high-z deselected standby x x x x h h high-z high-z deselected standby l h h h l x high-z high-z output disabled active l h h h x l high-z high-z output disabled active l h l h l h d out high-z lower byte read active l h l h h l high-z d out upper byte read active l h l h l l d out d out word read active l h x l l h d in high-z lower byte write active l h x l h l high-z d in upper byte write active l h x l l l d in d in word write active item symbol ratings unit voltage on any pin relative to v ss v in ,v out -0.2 to v cc +0.3v v voltage on v cc supply relative to v ss v cc -0.2 to 4.0v v power dissipation p d 1.0 w operating temperature t a -40 to 85 c item symbol ratings unit voltage on any pin relative to v ss v in ,v out -0.2 to v cc +0.3v (max. 3.6v) v voltage on v cc supply relative to v ss v cc -0.2 to 3.6v v power dissipation p d 1.0 w operating temperature t a -40 to 85 c
june 15, 2004 sram_type01_02a0 sram 155 advance information dc characteristics recommended dc operating conditions (note 1) notes: 1. t a = -40 to 85 c, unless otherwise specified. 2. overshoot: vcc+1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. capacitance (f=1mhz, t a =25 c) note: capacitance is sampled, not 100% tested dc operating characteristics common item symbol min ty p max unit supply voltage v cc 2.7 3.0 3.3 v ground v ss 0 0 0 v input high voltage v ih 2.2 - v cc +0.2 (note 2) v input low voltage v il -0.2 (note 3) - 0.6 v item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf item symbol test conditions min ty p (note) max unit input leakage current i li v in =v ss to v cc -1 - 1 a output leakage current i lo cs1#=v ih or cs2=v il or oe#=v ih or we#=v il or lb#=ub#=v ih , v io =v ss to v cc -1 - 1 a output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - - v
156 sram sram_type01_02a0 june 15, 2004 advance information dc operating characteristics 4m version f note: typical values are not 100% tested. dc operating characteristics 4m version g note: typical values are not 100% tested. item symbol test conditions min ty p (note) max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in vcc-0.2v, lb# 0.2v or/and ub# 0.2v - - 3 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs1# = v il , cs2=v ih , byte# = v ss or v cc , v in =v il or v ih , lb# 0.2v or/ and ub# 0.2v - - 22 ma standby current (cmos) i sb1 (note) cs1# v cc -0.2v, cs2 v cc -0.2v (cs1# controlled) or cs2 0.2v (cs2 controlled), byte# = v ss or v cc , other input =0~v cc - 1.0 (note) 10 a item symbol test conditions min ty p (note) max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in vcc-0.2v, lb# 0.2v or/and ub# 0.2v - - 4 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs1# = v il , cs2=v ih , byte# = v ss or v cc , v in =v il or v ih , lb# 0.2v or/ and ub# 0.2v - - 22 ma standby current (cmos) i sb1 (note) cs1# v cc -0.2v, cs2 v cc -0.2v (cs1# controlled) or cs2 0.2v (cs2 controlled), byte# = v ss or v cc , other input = 0~v cc - 3.0 (note) 10 a
june 15, 2004 sram_type01_02a0 sram 157 advance information dc operating characteristics 8m version c note: typical values are not 100% tested. dc operating characteristics 8m version d note: typical values are not 100% tested. item symbol test conditions min ty p (note) max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in vcc-0.2v, lb# 0.2v or/and ub# 0.2v - - 3 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs1# = v il , cs2=v ih , byte# = v ss or v cc , v in =v il or v ih , lb# 0.2v or/ and ub# 0.2v - - 22 ma standby current (cmos) i sb1 (note) cs1# v cc -0.2v, cs2 v cc -0.2v (cs1# controlled) or cs2 0.2v (cs2 controlled), byte# = v ss or v cc , other input = 0~v cc - - 15 a item symbol test conditions min ty p (note) max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in vcc-0.2v, lb# 0.2v or/and ub# 0.2v - - tbd ma i cc2 cycle time=min, i io =0ma, 100% duty, cs1# = v il , cs2=v ih , byte# = v ss or v cc , v in =v il or v ih , lb# 0.2v or/ and ub# 0.2v - - tbd ma standby current (cmos) i sb1 (note) cs1# v cc -0.2v, cs2 v cc -0.2v (cs1# controlled) or cs2 0.2v (cs2 controlled), byte# = v ss or v cc , other input = 0~v cc - - tbd a
158 sram sram_type01_02a0 june 15, 2004 advance information ac operating conditions test conditions test load and test input/output reference ? input pulse level: 0.4 to 2.2v ? input rising and falling time: 5ns ? input and output reference voltage: 1.5v ? output load (see figure 79): cl= 30pf+1ttl notes: 1. including scope and jig capacitance. 2. r1=3070 ? , r2=3150 ?. 3. v tm =2.8v. ac characteristics read/write characteristics (v cc =2.7-3.3v) figure 79. ac output load parameter list symbol speed bins units 70ns min max read read cycle time t rc 70 - ns address access time t aa - 70 ns chip select to output t co1 , t co2 - 70 ns output enable to valid output t oe - 35 ns lb#, ub# access time t ba - 70 ns chip select to low-z output t lz1 , t lz2 10 - ns lb#, ub# enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz1 , t hz2 0 25 ns ub#, lb# disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 10 - ns v tm (note 3) r1 (note 2) cl (note 1) r2 (note 2)
june 15, 2004 sram_type01_02a0 sram 159 advance information data retention characteristics (4m version f) notes: 1. cs1 controlled:cs1# v cc -0.2v. cs2 controlled: cs2 0.2v. 2. typical values are not 100% tested. write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns address set-up time t as 0 - ns address valid to end of write t aw 60 - ns lb#, ub# valid to end of write t bw 60 - ns write pulse width t wp 50 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 20 ns data to write time overlap t dw 30 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v (note 1) , v in 0v. byte# = v ss or v cc 1.5 - 3.3 v data retention current i dr v cc =3.0v, cs1# v cc -0.2v (note 1) , v in 0v - 1.0 (note 2) 10 a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - parameter list symbol speed bins units 70ns min max
160 sram sram_type01_02a0 june 15, 2004 advance information data retention characteristics (4m version g) notes: 1. cs1 controlled:cs1# v cc -0.2v. cs2 controlled: cs2 0.2v. data retention characteristics (8m version c) notes: 1. cs1 controlled:cs1# v cc -0.2v. cs2 controlled: cs2 0.2v. data retention characteristics (8m version d) notes: 1. cs1 controlled:cs1# v cc -0.2v. cs2 controlled: cs2 0.2v. timing diagrams item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v (note 1) , v in 0v. byte# = v ss or v cc 1.5 - 3.3 v data retention current i dr v cc =1.5v, cs1# v cc -0.2v (note 1) , v in 0v - - 3 a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v (note 1) . byte# = v ss or v cc 1.5 - 3.3 v data retention current i dr v cc =3.0v, cs1# v cc -0.2v (note 1) - - 15 a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v (note 1) , byte# = v ss or v cc 1.5 - 3.3 v data retention current i dr v cc =3.0v, cs1# v cc -0.2v (note 1) - - tbd a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - - figure 80. timing waveform of read cycle(1) (address controlled, cs#1=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il ) t aa t rc t oh address data out previous data valid data valid
june 15, 2004 sram_type01_02a0 sram 161 advance information notes: 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. figure 81. timing waveform of read cycle(2) (we#=v ih , if byte# is low, ignore ub#/lb# timing) figure 82. timing waveform of write cycle(1) (we# contro lled, if byte# is low, ignore ub#/lb# timing) high-z t rc t oh t aa t co1 t ba t oe t olz t blz t lz t ohz t bhz t hz t co2 address cs1# cs2 ub#, lb# oe# data out data valid t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z t cw(2) address cs1# cs2 ub#, lb# we# data in data out data undefined data valid
162 sram sram_type01_02a0 june 15, 2004 advance information figure 83. timing waveform of write cycle(2) (cs# controlled, if byte# is low, ignore ub#/lb# timing) notes: 1. a write occurs during the overlap (t wp ) of low cs1# and low we#. a write begins when cs1# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs1# goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs1# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs1# or we# going high. figure 84. timing waveform of write cycle(3) (ub#, lb# controlled) high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) address cs1# cs2 ub#, lb# we# data in data out data valid high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) t cw(2) address cs1# cs2 ub#, lb# we# data in data out data valid
june 15, 2004 sram_type01_02a0 sram 163 advance information figure 85. data retention waveform t sdr t rdr t sdr t rdr v cc 2.7v 2.2v v dr cs1# gnd cs1# controlled cs2 controlled v cc 2.7v v dr 0.4v gnd cs2 cs1# v cc - 0.2v data retention mode data retention mode cs2 0.2v
164 psram type 1 psram_type01_12_a0 june 8, 2004 advance information psram type 1 4mbit (256k word x 16-bit) 8mbit (512k word x 16-bit) 16mbit (1m word x 16-bit) 32mbit (2m word x 16-bit) 64mbit (4m word x 16-bit) features ? fast cycle times ?t acc < 70 ns ?t acc < 65 ns ?t acc < 60 ns ?t acc < 55 ns ? very low standby current ?i sb < 120 a (64m and 32m) ?i sb < 100 a (16m) ? very low operating current ? icc < 25ma functional description absolute maximum ratings mode ce# ce2/zz# oe# we# ub# lb# addresses i/o 1-8 i/o 9-16 power read (word) l h l h l l x dout dout i active read (lower byte) l h l h h l x dout high-z i active read (upper byte) l h l h l h x high-z dout i active write (word) l h x l l l x din din i active write (lower byte) l h x l h l x din invalid i active write (upper byte) l h x l l h x invalid din i active outputs disabled l h h h x x x high-z high-z i active standby h h x x x x x high-z high-z i standby deep power down h l x x x x x high-z high-z i deep sleep item symbol ratings units voltage on any pin relative to v ss vin, vout -0.2 to v cc +0.3 v voltage on v cc relative to v ss v cc -0.2 to 3.6 v power dissipation p d 1 w storage temperature t stg -55 to 150 c operating temperature t a -25 to 85 c
june 8, 2004 psram_type01_12_a0 psram type 1 165 advance information dc characteristics (4mb psram asynchronous) asynchronous performance grade -70 density 4mb psram symbol parameter conditions min max units v cc power supply 2.7 3.3 v v ih input high level 1.4 vccq v cc + 0.3 v v il input low level -0.3 0.4 v i il input leakage current vin = 0 to v cc 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a v oh output high voltage i oh = -1.0 ma v i oh = -0.2 ma 0.8 vccq i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma v i ol = 0.2 ma 0.2 i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma i standby standby current v cc = 3.0 v 70 a v cc = 3.3 v i deep sleep deep power down current xa i par 1/4 1/4 array par current xa i par 1/2 1/2 array par current xa
166 psram type 1 psram_type01_12_a0 june 8, 2004 advance information dc characteristics (8mb psram asynchronous) asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram symbol parameter conditions min max units min max units min max units v cc power supply 2.7 3.3 v 2.7 3.6 v 2.7 3.3 v v ih input high level 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v 1.4 v cc +0.3 v v il input low level -0.3 0.6 v -0.3 0.6 v -0.3 0.4 v i il input leakage current vin = 0 to v cc 0.5 a 0.5 a 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a 0.5 a 0.5 a v oh output high voltage i oh = -1.0 ma v cc -0.4 v v cc -0.4 vv i oh = -0.2 ma 0.8 v ccq i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma 0.4 v 0.4 vv i ol = 0.2 ma 0.2 i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma 23 ma 25 ma i standby standby current v cc = 3.0 v 60 a 60 a 60 a v cc = 3.3 v i deep sleep deep power down current xa xa xa i par 1/4 1/4 array par current xa xa xa i par 1/2 1/2 array par current xa xa xa
june 8, 2004 psram_type01_12_a0 psram type 1 167 advance information dc characteristics (16mb psram asynchronous) asynchronous performance grade -55 -70 density 16mb psram 16mb psram symbol parameter conditions minimum maximum units minimum maximum units v cc power supply 2.7 3.6 v 2.7 3.6 v v ih input high level 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v v il input low level -0.3 0.6 v -0.3 0.6 v i il input leakage current vin = 0 to v cc 0.5 a 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a 0.5 a v oh output high voltage i oh = -1.0 ma v cc -0.4 v v cc -0.4 v i oh = -0.2 ma i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma 0.4 v 0.4 v i ol = 0.2 ma i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma 23 ma i standby standby current v cc = 3.0 v 100 a 100 a v cc = 3.3 v i deep sleep deep power down current x a x a i par 1/4 1/4 array par current x a x a i par 1/2 1/2 array par current x a x a
168 psram type 1 psram_type01_12_a0 june 8, 2004 advance information dc characteristics (16mb psram page mode) page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram symbol parameter conditions min max units min max units min max units v cc power supply 2.7 3.3 v 2.7 3.3 v 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.2 vccq v -0.2 0.2 vccq v -0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 1a 1a 1a i lo output leakage current oe = v ih or chip disabled 1a 1a 1a v oh output high voltage i oh = -1.0 ma vv v i oh = -0.2 ma i oh = -0.5 ma 0.8 vccq 0.8 vccq 0.8 vccq v ol output low voltage i ol = 2.0 ma vv v i ol = 0.2 ma i ol = 0.5 ma 0.2 vccq 0.2 vccq 0.2 vccq i active operating current v cc = 3.3 v 25 ma 25 ma 25 ma i standby standby current v cc = 3.0 v a a a v cc = 3.3 v 100 100 100 i deep sleep deep power down current 10 a 10 a 10 a i par 1/4 1/4 array par current 65 a 65 a 65 a i par 1/2 1/2 array par current 80 a 80 a 80 a
june 8, 2004 psram_type01_12_a0 psram type 1 169 advance information dc characteristics (32mb psram page mode) page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram symbol parameter conditions min max units min max units min max units min max units v cc power supply 2.7 3.6 v 2.7 3.3 v 2.7 3.3 v 2.7 3.3 v v ih input high level 1.4 v cc + 0.2 v0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.4 v -0.2 0.2 vccq v-0.2 0.2 vccq v-0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 0.5 a 1 a 1 a 1 a i lo output leakage current oe = v ih or chip disabled 0.5 a 1 a 1 a 1 a v oh output high voltage i oh = -1.0 ma vv vv i oh = -0.2 ma 0.8 vccq i oh = -0.5 ma 0.8 vccq 0.8 vccq 0.8 vccq v ol output low voltage i ol = 2.0 ma vv vv i ol = 0.2 ma 0.2 i ol = 0.5 ma 0.2 vccq 0.2 vccq 0.2 vccq i active operating current v cc = 3.3 v 25 ma 25 ma 25 ma 25 ma i standby standby current v cc = 3.0 v a a a a v cc = 3.3 v 100 120 120 100 i deep sleep deep power down current 10 a 10 a 10 a 10 a i par 1/4 1/4 array par current 65 a 75 a 75 a 65 a i par 1/2 1/2 array par current 80 a 90 a 90 a 80 a
170 psram type 1 psram_type01_12_a0 june 8, 2004 advance information dc characteristics (64mb psram page mode) timing test conditions page mode performance grade -70 density 64mb psram symbol parameter conditions min max units v cc power supply 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 1a i lo output leakage current oe = v ih or chip disabled 1a v oh output high voltage i oh = -1.0 ma v i oh = -0.2 ma i oh = -0.5 ma 0.8 vccq v ol output low voltage i ol = 2.0 ma v i ol = 0.2 ma i ol = 0.5 ma 0.2 vccq i active operating current v cc = 3.3 v 25 ma i standby standby current v cc = 3.0 v a v cc = 3.3 v 120 i deep sleep deep power down current 10 a i par 1/4 1/4 array par current 65 a i par 1/2 1/2 array par current 80 a item input pulse level 0.1 v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc operating temperature -25c to +85c
june 8, 2004 psram_type01_12_a0 psram type 1 171 advance information output load circuit power up sequence after applying power, maintain a stable power supply for a minimum of 200 s after ce# > v ih . figure 86. output load circuit v cc 30 pf i/o 14.5k 14.5k output load
172 psram type 1 psram_type01_12_a0 june 8, 2004 advance information ac characteristics (4mb psram page mode) asynchronous performance grade -70 density 4mb psram 3 volt symbol parameter min max units read trc read cycle time 70 ns taa address access time 70 ns tco chip select to output 70 ns toe output enable to valid output 20 ns tba ub#, lb# access time 70 ns tlz chip select to low-z output 10 ns tblz ub#, lb# enable to low-z output 10 ns tolz output enable to low-z output 5ns thz chip enable to high-z output 020ns tbhz ub#, lb# disable to high-z output 020ns tohz output disable to high-z output 020ns toh output hold from address change 10 ns
june 8, 2004 psram_type01_12_a0 psram type 1 173 advance information write twc write cycle time 70 ns tcw chipselect to end of write 70 ns tas address set up time 0ns taw address valid to end of write 70 ns tbw ub#, lb# valid to end of write 70 ns twp write pulse width 55 ns twr write recovery time 0ns twhz write to output high-z 20 ns tdw data to write time overlap 25 ns tdh data hold from write time 0ns tow end write to output low-z 5 tow write high pulse width 7.5 ns other tpc page read cycle x tpa page address access time x twpc page write cycle x tcp chip select high pulse width x asynchronous performance grade -70 density 4mb psram 3 volt symbol parameter min max units
174 psram type 1 psram_type01_12_a0 june 8, 2004 advance information ac characteristics (8mb psram asynchronous) asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram 3 volt symbol parameter min max units min max units min max units read trc read cycle time 55 ns 70 ns 70 ns taa address access time 55 ns 70 ns 70 ns tco chip select to output 55 ns 70 ns 70 ns toe output enable to valid output 30 ns 35 ns 20 ns tba ub#, lb# access time 55 ns 70 ns 70 ns tlz chip select to low-z output 5 ns 5 ns 10 ns tblz ub#, lb# enable to low-z output 5 ns 5 ns 10 ns tolz output enable to low-z output 5ns5ns5ns thz chip enable to high-z output 020ns025ns 020ns tbhz ub#, lb# disable to high-z output 020ns025ns 020ns tohz output disable to high-z output 020ns025ns 020ns toh output hold from address change 10 ns 10 ns 10 ns
june 8, 2004 psram_type01_12_a0 psram type 1 175 advance information write twc write cycle time 55 ns 70 ns 70 ns tcw chip select to end of write 45 ns 55 ns 70 ns tas address set up time 0ns0ns0ns taw address valid to end of write 45 ns 55 ns 70 ns tbw ub#, lb# valid to end of write 45 ns 55 ns 70 ns twpwrite pulse width45ns55ns55ns twr write recovery time 0ns0ns0ns twhz write to output high-z 25 ns 25 20 ns tdw data to write time overlap 40 ns 40 ns 25 ns tdh data hold from write time 0ns0ns0ns tow end write to output low-z 555 tow write high pulse width x x ns x x ns x x ns other tpc page read cycle x x x tpa page address access time xxx twpc page write cycle x x x tcp chip select high pulse width xxx asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram 3 volt symbol parameter min max units min max units min max units
176 psram type 1 psram_type01_12_a0 june 8, 2004 advance information ac characteristics (16mb psram asynchronous) asynchronous performance grade -55 -70 density 16mb psram 16mb psram 3 volt symbol parameter min max units min max units read trc read cycle time 55 ns 70 ns taa address access time 55 ns 70 ns tco chip select to output 55 ns 70 ns toe output enable to valid output 30 ns 35 ns tba ub#, lb# access time 55 ns 70 ns tlz chip select to low-z output 5ns5ns tblz ub#, lb# enable to low-z output 5ns5ns tolz output enable to low-z output 5ns5ns thz chip enable to high-z output 025ns025ns tbhz ub#, lb# disable to high-z output 025ns025ns tohz output disable to high-z output 025ns025ns toh output hold from address change 10 ns 10 ns
june 8, 2004 psram_type01_12_a0 psram type 1 177 advance information write twc write cycle time 55 ns 70 ns tcw chipselect to end of write 50 ns 55 ns tas address set up time 0ns0ns taw address valid to end of write 50 ns 55 ns tbw ub#, lb# valid to end of write 50 ns 55 ns twp write pulse width 50 ns 55 ns twr write recovery time 0ns0ns twhz write to output high-z 25 ns 25 ns tdw data to write time overlap 25 ns 25 ns tdh data hold from write time 0ns0ns tow end write to output low-z 55 tow write high pulse width xxnsxxns other tpc page read cycle x x tpa page address access time xx twpc page write cycle x x tcp chip select high pulse width xx asynchronous performance grade -55 -70 density 16mb psram 16mb psram 3 volt symbol parameter min max units min max units
178 psram type 1 psram_type01_12_a0 june 8, 2004 advance information ac characteristics (16mb psram page mode) page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram 3 volt symbol parameter min max units min max units min max units read trc read cycle time 60 20k ns 65 20k ns 70 20k ns taa address access time 60 ns 65 ns 70 ns tco chip select to output 60 ns 65 ns 70 ns toe output enable to valid output 25 ns 25 ns 25 ns tba ub#, lb# access time 60 ns 65 ns 70 ns tlz chip select to low-z output 10 ns 10 ns 10 ns tblz ub#, lb# enable to low-z output 10 ns 10 ns 10 ns tolz output enable to low-z output 5ns5ns5ns thz chip enable to high-z output 0 5 ns 0 5 ns 0 5 ns tbhz ub#, lb# disable to high-z output 0 5 ns 0 5 ns 0 5 ns tohz output disable to high-z output 0 5 ns 0 5 ns 0 5 ns toh output hold from address change 5ns5ns5ns
june 8, 2004 psram_type01_12_a0 psram type 1 179 advance information write twc write cycle time 60 20k ns 65 20k ns 70 20k ns tcw chipselect to end of write 50 ns 60 ns 60 ns tas address set up time 0ns0ns0ns taw address valid to end of write 50 ns 60 ns 60 ns tbw ub#, lb# valid to end of write 50 ns 60 ns 60 ns twpwrite pulse width50ns50ns50ns twr write recovery time 0ns0ns0ns twhz write to output high-z 5ns 5ns 5ns tdw data to write time overlap 20 ns 20 ns 20 ns tdh data hold from write time 0ns0ns0ns tow end write to output low-z 555 tow write high pulse width 7.5ns7.5ns7.5ns other tpc page read cycle 25 20k ns 25 20k ns 25 20k ns tpa page address access time 25 ns 25 ns 25 ns twpc page write cycle 25 20k ns 25 20k ns 25 20k ns tcp chip select high pulse width 10 ns 10 ns 10 ns page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram 3 volt symbol parameter min max units min max units min max units
180 psram type 1 psram_type01_12_a0 june 8, 2004 advance information ac characteristics (32mb psram page mode) page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram 3 volt symbol parameter min max units min max units min max units min max units read trc read cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns taa address access time 65 ns 60 ns 65 ns 70 ns tco chip select to output 65 ns 60 ns 65 ns 70 ns toe output enable to valid output 20 ns 25 ns 25 ns 25 ns tba ub#, lb# access time 65 ns 60 ns 65 ns 70 ns tlz chip select to low-z output 10 ns 10 ns 10 ns 10 ns tblz ub#, lb# enable to low-z output 10 ns 10 ns 10 ns 10 ns tolz output enable to low-z output 5 ns 5 ns 5 ns 5 ns thz chip enable to high-z output 020ns 0 5ns 0 5ns0 5ns tbhz ub#, lb# disable to high-z output 020ns 0 5ns 0 5ns0 5ns tohz output disable to high-z output 020ns 0 5ns 0 5ns0 5ns toh output hold from address change 5 ns 5 ns 5 ns 5 ns
june 8, 2004 psram_type01_12_a0 psram type 1 181 advance information write twc write cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns tcw chipselect to end of write 55 ns 50 ns 60 ns 60 ns tas address set up time 0 ns 0 ns 0 ns 0 ns taw address valid to end of write 55 ns 50 ns 60 ns 60 ns tbw ub#, lb# valid to end of write 55 ns 50 ns 60 ns 60 ns twp write pulse width 55 20k ns 50 ns 50 ns 50 ns twr write recovery time 0 ns 0 ns 0 ns 0 ns twhz write to output high-z 5 ns 5 ns 5 ns 5 ns tdw data to write time overlap 25 ns 20 ns 20 ns 20 ns tdh data hold from write time 0 ns 0 ns 0 ns 0 ns tow end write to output low-z 55 5 5 tow write high pulse width 7.5 ns 7.5 ns 7.5 ns 7.5 ns other tpc page read cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tpa page address access time 25 ns 25 ns 25 ns 25 ns twpc page write cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tcp chip select high pulse width 10 ns 10 ns 10 ns 10 ns page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram 3 volt symbol parameter min max units min max units min max units min max units
182 psram type 1 psram_type01_12_a0 june 8, 2004 advance information ac characteristics (64mb psram page mode) page mode performance grade -70 density 64mb psram 3 volt symbol parameter min max units read trc read cycle time 70 20k ns taa address access time 70 ns tco chip select to output 70 ns toe output enable to valid output 25 ns tba ub#, lb# access time 70 ns tlz chip select to low-z output 10 ns tblz ub#, lb# enable to low-z output 10 ns tolz output enable to low-z output 5ns thz chip enable to high-z output 05ns tbhz ub#, lb# disable to high-z output 05ns tohz output disable to high-z output 05ns toh output hold from address change 5ns
june 8, 2004 psram_type01_12_a0 psram type 1 183 advance information timing diagrams read cycle write twc write cycle time 70 20k ns tcw chipselect to end of write 60 ns tas address set up time 0ns taw address valid to end of write 60 ns tbw ub#, lb# valid to end of write 60 ns twp write pulse width 50 20k ns twr write recovery time 0ns twhz write to output high-z 5ns tdw data to write time overlap 20 ns tdh data hold from write time 0ns tow end write to output low-z 5 tow write high pulse width 7.5 ns other tpc page read cycle 20 20k ns tpa page address access time 20 ns twpc page write cycle 20 20k ns tcp chip select high pulse width 10 ns figure 87. timing of read cycle (ce# = oe# = v il , we# = zz# = v ih ) page mode performance grade -70 density 64mb psram 3 volt symbol parameter min max units a ddress data out t rc t aa t oh data valid previous data valid
184 psram type 1 psram_type01_12_a0 june 8, 2004 advance information figure 88. timing waveform of read cycle (we# = zz# = v ih ) address lb#, ub# oe# data valid t rc t aa t co t hz t ohz t bhz t olz t oe t lz high-z data out t lb, t ub t blz ce#
june 8, 2004 psram_type01_12_a0 psram type 1 185 advance information figure 89. timing waveform of page mode read cycle (we# = zz# = v ih ) page address (a4 - a20) lb#, ub# oe# t aa t co t hz t ohz t bhz t olz t oe high-z data out t lb, t ub t blz, ce# word address (a0 - a3) t pa t rc t pgmax t pc
186 psram type 1 psram_type01_12_a0 june 8, 2004 advance information write cycle figure 90. timing waveform of write cycle (we# control, zz# = v ih ) figure 91. timing waveform of write cycle (ce# control, zz# = v ih ) addr es s dat a in ce# data valid t wc t aw t cw t wr t whz t dh high-z we# da ta out high-z t ow t as t wp t dw t bw lb#, ub# ad dr es s we# data valid t wc t aw t cw t wr t dh lb#, ub# dat a in high-z t as t wp t dw t bw da ta o ut t whz ce#
june 8, 2004 psram_type01_12_a0 psram type 1 187 advance information figure 92. timing waveform of page mode write cycle (zz# = v ih ) page a ddr es s (a4 - a 20) lb#, ub# we# t wp t cw t dw high-z dat a out t lbw, t ubw ce# wor d a ddr es s (a0 - a3 ) t wc t pwc t dh t pdw t pdh t pdw t pdh t as t pgmax
188 psram type 1 psram_type01_12_a0 june 8, 2004 advance information power savings modes (for 16m page mode, 32m and 64m only) there are several power savings modes. ? partial array self refresh ? temperature compensated refresh (64m) ? deep sleep mode ? reduced memory size (32m, 16m) the operation of the power saving modes ins controlled by the settings of bits contained in the mode register. this definition of the mode register is shown in figure 93 and the various bits are used to enable and disable the various low power modes as well as enabling page mode operation. the mode register is set by using the timings defined in figure xxx. partial array self refresh (par) in this mode of operation, the internal refresh operation can be restricted to a 16mb, 32mb, or 48mb portion of the array. the array partition to be refreshed is determined by the respective bit settings in the mode register. the register set - tings for the pasr operation are defined in table xxx. in this pasr mode, when zz# is active low, only the portion of the array that is set in the register is re - freshed. the data in the remainder of the array will be lost. the pasr operation mode is only available during standby time (zz# low) and once zz# is returned high, the device resumes full array refresh. all future pasr cycles will use the contents of the mode register that has been previously set. to change the ad - dress space of the pasr mode, the mode register must be reset using the previously defined procedures. for pasr to be activated, the register bit, a4must be set to a one (1) value, ?pasr enabled?. if this is the case, pasr will be acti - vated 10 s after zz# is brought low. if the a4 register bit is set equal to zero (0), pasr will not be activated. temperature compensated refresh (for 64mb) in this mode of operation, the internal refresh rate can be optimized for the op - eration temperature used and this can then lower standby current. the dram array in the psram must be refreshed internally on a regular basis. at higher temperatures, the dram cell must be refreshed more often than at lower tem - peratures. by setting the temperature of operation in the mode register, this refresh rate can be optimized to yield the lowest standby current at the given op - erating temperature. there are four diff erent temperature settings that can be programmed in to the psram. these are defined in figure 93 . deep sleep mode in this mode of operation, the internal re fresh is turned off and all data integrity of the array is lost. deep sleep is entered by bringing zz# low with the a4 reg - ister bit set to a zero (0), ?deep sleep enabled?. if this is the case, deep sleep will be entered 10 s after zz# is brought low. the device will remain in this mode as long as zz# remains low. if the a4 register bit is set equal to one (1), deep sleep will not be activated. reduced memory size (for 32m and 16m) in this mode of operation, the 32mb psram can be operated as a 8mb or 16mb device. the mode and array size are determined by the settings in the va register. the va register is set according to the fo llowing timings and the bit settings in the table ?address patterns for rms?. the rms mode is enabled at the time of zz
june 8, 2004 psram_type01_12_a0 psram type 1 189 advance information transitioning high and the mode remains active until the register is updated. to return to the full 32mb address space, the va register must be reset using the previously defined procedures. while operating in the rms mode, the unselected portion of the array may not be used. other mode register settings (for 64m) the page mode operation can also be enabled and disabled using the mode reg - ister. register bit a7 controls the operation of page mode and setting this bit to a one (1), enables page mode. if the register bit a7 is set to a zero (0), page mode operation is disabled. figure 93. mode register deep sleep enable/disabl e 0 = deep sleep enabled 1 = deep sleep disabled (default) par section 1 1 1 = top 1/4 array 1 1 0 = top 1/2 array 1 0 1 = top 3/4 array 1 0 0 = no par 0 1 1 = bottom 1/4 array 0 1 0 = bottom 1/2 array 0 0 1 = bottom 3/4 array 0 0 0 = full array (default) reserved must set to all 0 a21 - a8 a7 a6 a5 a4 a3 a2 a1 a0 page mode 0 = page mode disabled (default) 1 = page mode enabled te m p compensated refresh 1 0 = 15 o c 0 1 = 45 o c 0 0 = 70 o c 1 1 = 85 o c (default) array mode for zz# 0 = par (default) 1 = rms 64 mb 32 mb / 16 mb
190 psram type 1 psram_type01_12_a0 june 8, 2004 advance information figure 94. mode register update timings (ub#, lb#, oe# are don?t care) figure 95. deep sleep mode - entry/exit timings address zz# t wc t as ce# we# t zzwe t aw t wp t wr t cdzz zz# t zzmin t cdzz t r ce#
june 8, 2004 psram_type01_12_a0 psram type 1 191 advance information mode register update and deep sleep timings notes: 1. minimum cycle time for writing register is equal to speed grade of product. address patterns for pasr (a4=1) (64m) item symbol min max unit note chip deselect to zz# low t cdzz 5 ns zz# low to we# low t zzwe 10 500 ns write register cycle time t wc 70/85 ns 1 chip enable to end of write t cw 70/85 ns 1 address valid to end of write t aw 70/85 ns 1 write recovery time t wr 0 ns address setup time t as 0 ns write pulse width t wr 40 ns deep sleep pulse width t zzmin 10 s deep sleep recovery t r 150 s a2 a1 a0 active section address space size density 1 1 1 top quarter of die 300000h-3fffffh 1mb x 16 16mb 1 1 0 top half of die 200000h-3fffffh 2mb x 16 32mb 1 0 1 reserved 1 0 0 no pasr none 0 0 0 1 1 bottom quarter of die 000000h-0fffffh 1mb x 16 16mb 0 1 0 bottom half of die 000000h-1fffffh 2mb x 16 32mb 0 0 1 reserved 0 0 0 full array 000000h-3fffffh 4mb x 16 64mb
192 psram type 1 psram_type01_12_a0 june 8, 2004 advance information deep icc characteristics (for 64mb) address patterns for par (a3= 0, a4=1) (32m) address patterns for rms (a3 = 1, a4 = 1) (32m) item symbol te s t array partition ty p max unit pasr mode standby current i pasr v in = v cc or 0v, chip disabled, t a = 85c none 10 a 1/4 array 75 1/2 array 90 full array 120 item symbol max temperature ty p max unit temperature compensated refresh current i tcr 15c 50 a 45c 60 70c 80 85c 120 item symbol te s t ty p max unit deep sleep current i zz v in = v cc or 0v, chip in zz# mode, t a = 25c 10 a a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb x 0 0 full die 000000h - 1fffffh 2mb x 16 32mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb
june 8, 2004 psram_type01_12_a0 psram type 1 193 advance information low power icc characteristics (32m) address patterns for par (a3= 0, a4=1) (16m) address patterns for rms (a3 = 1, a4 = 1) (16m) low power icc characteristics (16m) item symbol te s t array partition ty p max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 65 a 1/2 array 80 a rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 4mb device 40 a 8mb device 50 a deep sleep current i zz v in = v cc or 0v, chip in zz mode, t a = 85 o c 10 a a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 00000h - 0ffffh 256kb x 16 4mb 0 1 0 one-half of die 00000h - 7ffffh 512kb x 16 8mb x 0 0 full die 00000h - fffffh 1mb x 16 162mb 1 1 1 one-quarter of die c0000h - ffffh 256kb x 16 4mb 1 1 0 one-half of die 80000h - 1fffffh 512kb x 16 8mb a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 00000h - 0ffffh 256kb x 16 4mb 0 1 0 one-half of die 00000h - 7ffffh 512kb x 16 8mb 1 1 1 one-quarter of die c0000h - fffffh 256kb x 16 4mb 1 1 0 one-half of die 80000h - fffffh 512kb x 16 8mb item symbol te s t array partition ty p max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 65 a 1/2 array 80 rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 4mb device 40 a 8mb device 50 deep sleep current i zz v in = v cc or 0v, chip in zz# mode, t a = 85 o c 10 a
194 revision summary s71pl254/127/064/032j_00_a6 november 22, 2004 advance information revision summary revision a (may 3, 2004) initial release. revision a1 (may 6, 2004) mcp features corrected the high performance access times. connection diagrams added reference points on all diagrams. ordering information corrected package types. corrected the description of product family to page mode flash memory. psram type 1 corrected the description of the 8mb device to 512kb word x 16-bit. psram type 6 corrected the description of the 2mb device to 128kb word x 16-bit. corrected the description of the 4mb device to 256kb word x 16-bit. revision a2 (may 11, 2004) general description corrected the tables to reflect accurate device configurations. revision a3 (june 16, 2004) ordering information corrected the valid combinations tables to reflect accurate device configurations. sram new section added. revision a4 (july 16, 2004) global changes global change of fasl to spansion. global change to remove space between m and mb callouts. ?32mb flash memory? on page 2 replaced ?S71PL032J08-07? with ?S71PL032J08-0b?. replaced ?S71PL032Ja0? with ?S71PL032Ja0-07?. added row with the following content: S71PL032Ja0-08; 65; 16mb psram; 70; psram3; tlc056. ?64mb flash memory? on page 2 replaced ? s71pl064j08-0k? with ?s71pl064j08-0b?. replaced ? s71pl064j08-0p? with ?s71pl064j08-0u?. deleted ?s71pl064j80-05? row. replaced ? s71pl064ja0-07? with ?s71pl064ja0-0k?.
november 22, 2004 s71pl254/127/064/032j_00_a6 revision summary 195 advance information replaced ? s71pl064ja0-0z? with added row with the following content: s71pl064jb0-07; 65; 32m psram; 70; psram 1; tlc056. ?32mb flash memory? on page 2 replaced ? S71PL032Ja0-08? with ?S71PL032Ja0-0f?. ?64mb flash memory? on page 2 replaced ? S71PL032Ja0-07? with ?S71PL032Ja0-0k?. ?128mb flash memory? on page 3 added row with the following content: s71pl127jb0-9; 65; 32m psram; 70; psram; tla064. replaced ?s71pl127jb0-97? with ? s71pl127jb0-9z?. added row with the following content: s71pl127jc0-97; 65; 64m psram; 70; psram1; tla064. replaced ? s71pl127jc0-9p? with ?s71pl127jc0-9z?. in the s71pl254jb0-tb row changed psram type from ? psram3? to ?psram2?. ?256mb flash memory (2xs29pl127j)? on page 3 added row with the following content: s71pl254jb0-tb; 65; 32m psram; 70; psram3; fta084. added row with the following content: s71pl254jc0-tb; 65; 64m psram; 70; psram2; fta084. ?connection diagram (s71pl127j)? on page 11 updated pins d8, d9, and l5. added notes 2 and 3 to drawing. ?connection diagram (s71pl254j)? on page 12 updated pins d8 and d9. added note 2 to drawing. ?S71PL032J valid combinations? on page 15 changed S71PL032J08 (p)sram type access time (ns) from ?sram1? to ?sram2? (4 changes made in table). changed S71PL032Ja0 (p)sram type access time (ns) from ?sram3 / 70? to psram3 /70?. deleted all cells with the following collaborated text: ?baw,bfw, bai. bfi?. merged previous place holder with cell above. ?s71pl064j valid combinations? on page 16 in (p)sram type/access time (ns) changed all instances of ?stet? to ?psram1/ 70?. in package modifier/model number chan ged all instances of ?stet? to ?07?. added row to baw package and temperature sections with the following content: s71pl064jb0; 07; 65 (previously inclusive); psram1/70. ?s71pl127j valid combinations? on page 17 changed the s71pl127ja0 package modifier/model number from ?9z? to ?9p? (4 instances).
196 revision summary s71pl254/127/064/032j_00_a6 november 22, 2004 advance information added 4 rows with the following content: s71pl127jc0; 97; psram1/70. ?s71pl254j valid combinations? on page 18 added 4 rows with the following content: s71pl254jc0; tb; psram2/70. added 4 rows with the following content: s71pl254jb0; tb; psram2/70. ?s71pl254/127/064/032j based mcps? on page 1 added 254m to megabit indicator. added 16 to cmos indicator. revision a5 (september 14, 2004) product selector guide updated the 128mb flash memory table. valid combinations table updated the s71pl127j valid combinations table. revision a6 (november 22, 2004) product selector guide updated the 32mb and 64mb tables. valid combinations tables updated the 32mb and 64mb combinations . physical dimensions added the tsb064 package. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above-men - tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au - thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or disc ontinue work on any product without notice. the information in t his document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 spansion llc. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and expressfl ash are trademarks of span - sion llc. other company and product names used in this publication are for identification purposes only and may be trademarks o f their respective compa - nies.


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